Commit Graph

41 Commits

Author SHA1 Message Date
David B. Kinder 505cc2bb0e doc: use :zephyr_file: where appropriate
A new role :zephyr_file: is available that renders to a link to the file
or folder in GitHub.  Find appropriate references using :file: and
convert to :zephyr_file: to take advantage of its linking capability.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2019-03-09 09:50:27 -05:00
Anas Nashif acaae579cc doc: boards: make board images consistent with board name
Having the image use the same name will help us script listing the
boards.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-02-10 17:48:08 -05:00
Anas Nashif 0e4ff809d7 doc: boards: move all board docs to be index.rst
Be consistent in how board docs are named and move all to index.rst.
This will make the URL to the board documentation predictable and easier
to remember.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-02-09 17:22:08 -06:00
Anas Nashif 28b2f32967 boards: fix intro text for many boards
The phrase "Zephyr applications use the ..." in many boards and
inconsistently. This is just to say what is the board identify is.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-02-09 17:22:08 -06:00
Kumar Gala 31503a868b arch: xtensa: dts: Move HAS_DTS to arch level
Now that all supported xtensa boards use DTS we can move the Kconfig
setting to the arch level.  Remove HAS_DTS from board Kconfig files.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-02-01 12:45:29 -06:00
Savinay Dharmappa 40e0f18e21 dts: qemu_xtensa/xt-sim: Enable device tree support
patch enables dts support for boards qemu_xtensa and xt-sim

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2019-02-01 07:49:28 -06:00
Kumar Gala 758d5b14a9 boards: Remove board.h from boards that don't need it
These boards don't need board.h to work so remove it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-14 06:44:02 -06:00
Anas Nashif cea0b3a9c2 xtensa: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Ulf Magnusson a3128e6a2c boards: defconfig: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Rajavardhan Gundi 0090fd4d15 intel_s1000: create xt-sim_intel_s1000_defconfig
Create xt-sim_intel_s1000_defconfig to build intel_s1000 SoC
for simulator.

Change-Id: I938bc397ed636b333a14a715a03653de7f3e9351
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Anas Nashif 7ee8bb9677 build: deprecate ZEPHYR_GCC_VARIANT
We want to support other toolchain not based on GCC, so the variable is
confusing, use ZEPHYR_TOOLCHAIN_VARIANT instead.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-13 07:44:45 -08:00
Marti Bolivar e33ec242fd scripts: refactor flash/debug scripts to remove "shell"
The Python-based runners have replaced the old shell scripts. Refactor
the build system accordingly:

- FLASH_SCRIPT is now BOARD_FLASH_RUNNER
- DEBUG_SCRIPT is now BOARD_DEBUG_RUNNER

The values, rather than being the names of files, are now the names of
runners in scripts/support/runner. They are still short, descriptive
names like "openocd", "jlink", "em-starterkit", etc.

Adjust the zephyr_flash_debug.py call and runner internals
accordingly. Have each runner class report a name and the commands it
can handle. This lets us move some boilerplate from each do_run()
method into the common run() routine, and enables further improvements
in future patches.

The handles_command() method is temporary, and will be replaced by a
more general mechanism for describing runner capabilities in a
subsequent patch. The initial use case for extending this is to add
device tree awareness to the runners.

To try to avoid user confusion, abort the configuration if an
xxx_SCRIPT is defined.

Signed-off-by: Marti Bolivar <marti@opensourcefoundries.com>
2017-12-15 09:57:30 -05:00
Anas Nashif 429c2a4d9d kconfig: fix help syntax and add spaces
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-13 17:43:28 -06:00
Marti Bolivar b4842d5339 doc: boards: xtensa: convert make to cmake
Use zephyr-app-commands appropriately.

Signed-off-by: Marti Bolivar <marti@opensourcefoundries.com>
2017-11-10 18:35:50 -05:00
Sebastian Bøe 0829ddfe9a kbuild: Removed KBuild
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-11-08 20:00:22 -05:00
Sebastian Bøe 12f8f76165 Introduce cmake-based rewrite of KBuild
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.

Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.

This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.

For users that just want to continue their work with minimal
disruption the following should suffice:

Install CMake 3.8.2+

Port any out-of-tree Makefiles to CMake.

Learn the absolute minimum about the new command line interface:

$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..

$ cd build
$ make

PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html

Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-11-08 20:00:22 -05:00
Anas Nashif 0a38ce0395 boards: xt-sim: make board depend on SIMULATOR_XTENSA
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 16:29:55 -04:00
Anas Nashif 39cc489e01 board: xt-sim: add as a default test platform
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-16 13:05:54 -04:00
Anas Nashif 3b6e9092b3 boards: xt-sim: add definition for supported configurations
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-16 13:05:54 -04:00
Leandro Pereira 27ea2d8eb7 arch: xtensa: Convert Xtensa port to use gen_isr_table
The Xtensa port was the only one remaining to be converted to the new
way of connecting interrupts in Zephyr.  Some things are still
unconverted, mainly the exception table, and this will be performed
another time.

Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since
IRQs can't change priority on Xtensa: while the architecture has the
concept of interrupt priority levels, each line has a fixed level and
can't be changed.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
David B. Kinder 62a0cd246d doc: fix uses of back quotes in documentation
ReST defines interpreted text roles where text enclosed by single quotes
can be "intrepreted", for example :ref:`some name` becomes a link to
a label anywhere in the doc set named "some name", :c:func:`funcname()`
becomes a link to the API documentation for "funcname", and
:option:`CONFIG_NAME` becomes a link to, in our case, the documentation
for the generated Kconfig option.

This patch fixes uses of `some name` (without a role) by either adding
an explicit role, or changing to ``some name``, which indicates inline
code block formatting (most likely what was intended).

This is a precursor to changing the default behavior of interpreted
text to treat `some name` as :any:`some name` (as configured in
doc/conf.py), which would attempt to create a link to any available
definition of "some name".

We may not change this default role behavior, but it becomes an option
after the fixes in this patch.  In any case, this patch fixes incorrect
uses of single-quoted text (possibly introduced because GitHub's
markdown language uses single-quoted text for inline code formatting).

Jira: ZEP-2414

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-08-03 11:08:23 -04:00
Anas Nashif 295897c191 boards: add board meta-data
Add board metadata to be consumed by the sanitycheck script to provide
better matching with testcases and to test based on features declated in
the board files.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-21 20:56:53 -04:00
David B. Kinder 342bdda760 doc: spelling fixes in samples/ and boards/
regular spelling check on .rst files

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-06-12 18:28:08 -04:00
Andrew Boie 4f69bdaa0d sanitycheck: build more Xtensa SOCs
Now that we can specify what toolchain is intended for each
SOC, enable some more SOCs to be built.

A full sanitycheck run will require the installation of both
RF-2016.4 and RG-2016.4 releases.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-18 07:18:36 -04:00
Andrew Boie fe70b0876f xt-sim: don't depend on sample_controller SOC
The xtensa simulator can in fact simulate a variety of Xtensa SOCs.
Fixes build for alternate xt-sim_* defconfigs.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-15 15:04:40 -04:00
Andrew Boie 3ddd7f274e xt-sim: fix board definition, rename
The xt-sim defconfigs were selecting CONFIG_SIMULATOR_XTENSA instead
of CONFIG_BOARD_SIMULATOR_XTENSA.

Fix defconfigs and rename to CONFIG_BOARD_XT_SIM to ease any future
confusion between these similarly named defconfigs.

CONFIG_SIMULATOR_XTENSA is automatically set by xt-sim's
Kconfig.defconfig, it doesn't need to be explicitly specified in the
defconfigs themselves.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-15 15:04:40 -04:00
Anas Nashif f628c12b04 xtensa: rename SOC_SAMPLE_CONTROLLER
SOC_SAMPLE_CONTROLLER option name is too generic, make it Xtensa
specific to avoid confusion.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-05-12 07:00:04 -04:00
Anas Nashif 09b239102a xtensa: xt-sim: mark it as a board with simulator features
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-05-11 16:51:56 -04:00
Andrew Boie 18c949c9c9 xtensa: remove xt-sim_XRC_D2PM
This core configuration was removed from the tree since it cannot
implement irq_offload().

Remove an orphaned block in xtesna.ini.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 12:47:23 -04:00
David B. Kinder 2f41cb8329 doc: misspelling and UTF-8 fixes
More general spelling fixes, and cleaning up stray UTF-8 characters
such as curly-quotes, em- and en-dashes.  Use replacement strings
for |reg| and |trade|.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-05-09 20:15:49 -04:00
Mazen NEIFER 37352c809e xtensa port: Added documentation for xt-sim board.
Issue: ZEP-1899

Change-Id: I4cf2878468e8c1c9703a2af13d9c2b3ac6f78042
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-20 21:07:15 +00:00
Andrew Boie 6311ede125 xtensa: remove hifi_mini sim target
The core build in the SDK does not have a timer, making it impossible
to use this core with most of the sanity checks. We are working on
getting a special package of cores for Zephyr which meet our build
requirments; until then, remove this core as it doesn't build.

Change-Id: I3fa201f3c6b5724501e8cb1e1b8ba631436ebc23
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-13 11:45:52 -07:00
Andrew Boie 6922a22c28 xtensa: add simulator targets for more SOCs
Change-Id: Ibceaf01ed71783c597b030bcc5778da6a03e5699
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-13 12:42:07 +00:00
Andrew Boie d73641c50b xt-sim: remove extraneous C file
Change-Id: I8f2ac2e743e57e6a591b2f995fbef97ecfebf46e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-13 12:42:06 +00:00
Andrew Boie 11ee791b32 xtensa: build similar to other Zephyr arches
* CONFIG_SOC is now properly set and we do not need a separate
  XTENSA_CORE build variable

* Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed

* There is no default SOC selection, it is now done explicitly in
  the board's defconfig

* CONFIG_<board name> now renamed to CONFIG_SOC_<board name in
  uppercase> to conform to established style.

Issue: ZEP-1711
Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-13 12:42:06 +00:00
Andrew Boie 3a29b9cefa xt-sim: set default stack size for IPM console receiver
The default of 512 is insufficient.

Change-Id: I7dd1cca89d1f289ceb87aee8e8a80719846d139c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-03-06 16:58:21 +00:00
Andrew Boie eb50958266 xt-sim: add support for 'make debug'
Change-Id: I60b64c6b8c83e1e1c49d8cb2c5f857faee88a7a0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:01 -08:00
Andrew Boie 55acd15cc8 xt-sim: enable use of xtensa simulator with 'make run'
Change-Id: I450f24de73dc710ab3875b010ecf48e44370cfc0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER 03857ccb23 Xtensa port: Enable console when building for Xtensa simulator as board.
Change-Id: I48f25b7c7bb36bd7248e7d9e6718bf365eac56d9
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Andrew Boie aa3ab35c88 xtensa: fixup license identifiers
Master branch changed requirements for license headers while this
branch has been in development.

Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER 4db0805ad0 Xtensa port: Added board config files for Xtensa simulator paltform
This platform is not a real board but let user handle the xtensa
simulator just like a board.
This is needed until a qemu like simulaotr is added to Xtensa.

Change-Id: I54ab28e86eea956cf85af3ee9b4a10f0d531e54d
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:26 -08:00