Commit Graph

6 Commits

Author SHA1 Message Date
Erwan Gouriou 141b6500c9 soc: stm32h7: Add support for Cortex-M4 core
Add support for C-M4 core on STM32H7 series.
It is enabled in Dual core context with 2 alternatives boot methods:
* Boot CM4 CM7: Both core boot at reset, then CM4 enters Stop mode.
CM7 performs system configuration then finally wakes up CM4
* Boot CM7, CM4 Gated: Only CM7 boots at reset. Once done with
system configuration it triggers (requires option byte update)

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Erwan Gouriou fda2ea7253 drivers/serial: stm32: Add support for STM32H7 series
Add needful to enable uart on STM32H7.
This mostly impact dts but as well soc for fixup.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Erwan Gouriou d185ec4cff drivers/gpio: Add support on STM32H7 series
Add GPIO support on STM32H7.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Erwan Gouriou 80278f7a48 drivers/interrupt_controller: stm32: Add support for stm32h7
Add bare minimum to enable EXTI on STM32H7,
in single core configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Erwan Gouriou 2805ea9193 drivers/clock_control: STM32H7 support
Provide basic clock control driver for STM32H7.
Bus clock activation is done through CM7 and CM4 common registers
so we don't have to care to the CPU Id before accessing.
Accesses are not protected for now. Only possible configuration
is system clock source set to HSE driven PLL.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Erwan Gouriou ef35fbcf42 soc/arm: Provide basic support for STM32H7 series
Enable basic support to STM32H7, in single core configuration (M7).

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00