For the SoCs in which all the boards for that platform are using dts we
can remove the Kconfig bits that are now coming from device tree.
Change-Id: Iccf4c84beb83fa1c516b6166f94de37b4a0162ae
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As part of the transition to Device Tree, a temporary
HAS_DTS configuration variable, and a .fixup file per board
with symbol aliases were added.
This patch removes the cc32xx related fixup file
definitions, except for those used additionally outside
the cc32xx drivers.
Since cc32xx has DTS files, and since HAS_DTS will always be true,
it also removes the 'if !HAS_DTS' blocks from the cc32xx Kconfig
files.
Change-Id: I1c1b9f734795f523342f82ab32f2a38983812c0b
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move back to getting the number of IRQs from Kconfig. We do this
because the number of IRQs should really just be determined by scanning
the device tree and figuring out the highest IRQ value used.
Change-Id: I8e0dbec1d9d036d4e899b237c4dc7d833c422e18
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Cortex-M4 of the STM32F4 family has an FPU. Enable the FPU support
by selecting CPU_HAS_FPU.
Change-Id: Iddae9c547df6e010562649eb0997dc61563c8fc4
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The comment refers to STM32F1 instead of STM32F4.
Change-Id: Ide116b712146f87a6f4d2aaafea8bd181c4d9397
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The current implementation of stm32_gpio_set() uses the GPIO output data
register to change the state of individual GPIOs. The generated
assembler needs at least 3 instructions: load / modify / store.
This opens a small race window, for example if a thread and an
interrupt both try to change the state of the same GPIO bank.
Use the GPIO bit set/reset register to perform the atomic change without
locking.
This also has the benefit of a more optimised implementation, which can
be useful for GPIO-intensive work. Compare the new version:
08000c98 <stm32_gpio_set>:
8000c98: f001 010f and.w r1, r1, #15
8000c9c: 2301 movs r3, #1
8000c9e: b902 cbnz r2, 8000ca2 <stm32_gpio_set+0xa>
8000ca0: 3110 adds r1, #16
8000ca2: 408b lsls r3, r1
8000ca4: 6183 str r3, [r0, #24]
8000ca6: 2000 movs r0, #0
8000ca8: 4770 bx lr
and the old one:
08000c98 <stm32_gpio_set>:
8000c98: 2301 movs r3, #1
8000c9a: f001 010f and.w r1, r1, #15
8000c9e: fa03 f101 lsl.w r1, r3, r1
8000ca2: 6943 ldr r3, [r0, #20]
8000ca4: b10a cbz r2, 8000caa <stm32_gpio_set+0x12>
8000ca6: 4319 orrs r1, r3
8000ca8: e001 b.n 8000cae <stm32_gpio_set+0x16>
8000caa: ea23 0101 bic.w r1, r3, r1
8000cae: 6141 str r1, [r0, #20]
8000cb0: 2000 movs r0, #0
8000cb2: 4770 bx lr
Change-Id: Ie5800d1c345016028d1b9a099f5d74cac35f592a
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
In prep for supporting the older KL2x SoCs that use a different SPI
block, rename the current SPI driver to DSPI to match what the MCUX HAL
defines it as.
Change-Id: I9097580df5fca649ab6fd9a38212fced0b1ea6ed
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds the necessary changes to enable use of DTS for
generating required build information.
Change-Id: I0d7aa15488339a425ffe57b6354992851212f7f3
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The previous file contained erroneous values of the number of IRQs
in these socs.
Change-Id: Ie7d2c19d86e247599f4924b95d9330175140d894
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
The current nordic hal layer in ext/ requires additional macros to
include the correct files. This will be corrected in an upcoming version
of the hal layer itself but for now add the required macros so that
users can benefit from the hal peripheral code.
Change-Id: I95127d0a98d7e882fdc779f961718fa223d504eb
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
In Atmel SAM Family of MCUs, the watchdog is enabled by default at boot.
The watchdog once disabled, cannot be re-enabled back without a reset.
Hence disabling the Watchdog needs to be handled via the Watchdog driver.
Tested on Atmel SAMV71 Xplained Ultra Evaluation Kit.
Jira: ZEP-1684
Change-Id: I5682c3f007a846b064b8d16abf0d9b67d4c8e7d6
Signed-off-by: Souvik K Chakravarty <souvik.k.chakravarty@intel.com>
Help text in Kconfig files should be indented with <tab><space><space>.
Change-Id: Iefa5c8f4bfe329b4ee754ebfe43766f445432184
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
Provide a random driver wrapped around the MCUX TRNG driver.
Change-Id: Icbd7ab587aa18ecbd7eae52290aaa5d8ee504cf2
Origin: Original
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
MCUX contains more than one type of random number generator,
so refrect this in config and file names.
Change-Id: Iba4482a1ae41f35d471686f8b159c113147c4df8
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
Cube HAL implements timeout based on 1ms tick.
This commit allows Cube HAL to get Zephyr system clock.
Change-Id: I9a59edcf6fa8e0ebfd5040348db537dadd9fcdfa
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to support the discovery STM32F4 and STM32F429 boards,
it is necessary to make these socs available.
Change-Id: I351d294fb02c4385f291a6e258a3f7d81e85627e
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
The wrong UART was set on for the qemu_cortex_m3 slip (uart pipe) device
Change-Id: If6d6af0f32ef02ccc559cd1fff90ea499cc378c4
Signed-off-by: Richard Peters <mail@richardpeters.de>
Pin number should be decremented by 8 if the pin
refers to the GPIOx_AFRH register.
Change-Id: I76e960f3b4adc3c2139ef5a88f15dbe98603228e
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
Following activation of Cube LL based clock control driver,
this commits cleans up the useless structures for RCC definitions
and remove code relative to native F3 Clock control driver.
Change-Id: I6f3ee44adb09adc52927eb4b05f8a829665eb96d
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following activation of Cube LL based clock control driver,
this commits cleans up the useless structures for RCC definitions
and remove code relative to native L4 Clock control driver.
Change-Id: Ic0408d5f5ec66651d46d13dfaf447da2666367cd
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introduction of STM32Cube based clock control driver for
stm32 family, provide its support on stm32f3x soc.
Clean up will have to be done afterwards.
Change-Id: I20480579f12a6fc1f1f6a51589981ac3f1d63ef0
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introduction of STM32Cube based clock control driver for
stm32 family, provide its support on stm32l4x soc.
Clean up will have to be done afterwards.
Change-Id: I979a4169148c5fe5a0693d182d2d17f9ffaf1c77
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch adds the base DTS support for the KW41Z Freedom board. The
initial set of changes include SRAM, FLASH, IRQ controller and LPUART
support.
Change-Id: Ic68c4959ddad0c5cfe70d5576a0e58372b93ec9d
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
This patch adds DTS support to the ARM CMSDK UART driver. The DTS
currently specifies the IRQ, IRQ PRIO, and base address of the port.
Change-Id: I8e5bc81c013958be4297d563495bf126b53a83a9
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the base DTS support for the V2M Beetle board. The
initial set of changes include SRAM, FLASH, and IRQ controller support.
Change-Id: I06685622b9c57ac358544c71350074ce06e3371e
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds all the necessary changes to enable use of DTS for
generating required build information.
Change-Id: Ia476fbb14c7d9d6b9db3340c73f599556a880da3
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch ifdef's out information that would be redefined by
information generated from DTS. This patch also fixes up the serial
drives to work properly with the DTS generated information.
Change-Id: I912ccf35be23c107705a4866e5a68b3b51154ffa
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds DTS support and related files for the NXP Kinetis
platform. The DTS files contain the base definitions for the hardware
nodes on Kinetis platforms. The YAML files provide the definitions of
the contents of the DTS nodes.
The Kconfig changes were put in place to allow for the conversion of
existing drivers. Once those drivers are modified, the Kconfig options
that are replaced by the DTS information will be removed.
Change-Id: If110fffa99c0b12471cf2df206da6687277e4756
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This is a zero-copy networking implementation of Ethernet driver.
Limitations:
- one shot PHY setup, no support for PHY disconnect/reconnect
- no support for devices with DCache enabled due to missing
non-cacheable RAM regions in Zephyr.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1492
Change-Id: Ib944f91193efbd12c1142b0bcf1f635388bf1b87
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added basic USART driver for Atmel SAM MCU family. USART is a very
comprehensive module, currently only basic features sufficient to
support printf functionality are implemented by this driver.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Ia9710e4069243fb6c30de45953dfc1fe1266b63a
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Added common, internal, always available SAM HAL drivers: pmc, gpio.
Note: these drivers are meant to be used by other SAM drivers, not by
a user space program directly.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: I00cca358f27790dc94cf79f840584b85ff5191f6
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Added support for early SoC configuration which does not belong
conceptually to system initialization. ERASE, JTAG TDI pins are
currently configured here.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Id51adddb4c7cce22907af214461d75db83df129a
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added support for Atmel SAM E70 (Cortex-M7) MCU:
- Kconfig files
- device start-up code
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Ide4fd5dadd94897303090a6507b8d048773b645e
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
A number of SoCs clear out the Mem/Bus/Usage and Hard Fault exceptions
during init. Lets refactor that into a common function so we don't have
to keep duplicating it over and over.
Change-Id: Ida908a9092db37447abcf3c9872f36937982f729
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch fixes the UART4 base address on the ARM MPS2 platform.
Change-Id: I14bf2a4dc2378d4b2c4295a75cd68c6c895fbd60
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds the configuration parametes required to enable CMSDK
(Cortex-M System Design Kit) Drivers at MPS2 soc level.
It provides as well the definitions for the MPS2 System Control
registers.
Change-Id: I06181dcfeb4fb887425b85ec9a99c268c857a34e
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Adds initial support for the kw41z SoC. This is the first SoC in the
Kinetis W (wireless connectivity) series added to Zephyr. The kw41z
integrates a 2.4 GHz radio transceiver, BLE link layer hardware, and an
802.15.4 packet processor with an ARM Cortex M0+. It has 512 KB flash,
128 KB SRAM, and can run the system clock at up to 48 MHz.
This SoC currently has mcux shim drivers for lpuart (serial), gpio,
pinmux, i2c, and flash.
Jira: ZEP-1389
Change-Id: I8cff6d203867ba3ace7e05c36441dc8f3cbca8d8
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Renames the flash security section so it makes sense for other Kinetis
devices, not just k64. In Kinetis reference manuals, this section is
referred to as the 'flash configuration field'.
Change-Id: I2b7c7cc1ec2541419d77878d367d96c9ceb7a0cf
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a shim layer around the mcux lpuart driver to adapt it to the Zephyr
serial interface.
NXP has multiple uart hardware blocks that implement different features
and have different register maps. The k64 has a uart block called
'uart', while the kw41 has a uart block called 'lpuart' (low power
uart). The MCUXpresso SDK provides separate drivers for each type of
uart block but with similar software interfaces. As a result, there are
also separate shim drivers in Zephyr. There is a 1:1:1 relationship
between hardware block, mcux driver, and mcux shim driver.
Because we now have two mcux shim drivers for the uart interface, a new
naming convention is created:
<interface>_mcux_<hw block>
Where <interface> is the name of the Zephyr interface, in this case
'uart'. This convention is not new.
<hw block> is the name of the NXP hardware block, in this case 'lpuart'.
This is the new part, and distinguishes different hardware blocks
for the same interface.
Change-Id: I3a80b9bffa116bbb2b02ee950d4bdd79a19a4edc
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Nordic Semiconductor's Software Development Kit's HAL layer
provides a set of low-level header and sourcefiles that give access
to the different hardware peripherals of Nordic ICs.
This patch includes the new files in the build and refactors the Kconfig
and Kbuild files in ext/hal/nordic to acommodate for the presence of the
new HAL layer.
Change-Id: Ie8e1a4c9fcc7e9058a9d16a2692ef1789603aa53
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The STM32 GPIO driver extended the generic GPIO driver interace with
the concept of OPEN_DRAIN. There is previous discussion about
representing such concepts in the GPIO interface in a more general
fashion here:
https://lists.zephyrproject.org/archives/list/devel@lists.zephyrproject.org/thread/6DCFUAKCOOOBHUO3ZK45ES6IQXOEOFWN/
The DRIVE STRENGTH interface supports the concepts of OPEN DRAIN and
other variants supports by other vendors hardware.
Adjust the STM32 GPIO driver to use the DRIVE STRENGTH interface. A
following patch will address the simplication of gpio.h
Change-Id: I56b0792ec2b21f1adc673dff019288dc8573d005
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This avoids asm files from having to explicitly define the _ASMLANGUAGE
symbol themselves.
Change-Id: I71f5a169f75d7443a58a0365a41c55b20dae3029
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
Support using CMSIS defines and functions, we either pull the expect
defines/enum from the SoC HAL layers via <soc.h> for the SoC or we
provide a default set based on __NVIC_PRIO_BITS is defined.
We provide defaults in the case for:
IRQn_Type enum
*_REV define (set to 0)
__MPU_PRESENT define (set to 0 - no MPU)
__NVIC_PRIO_BITS define (set to CONFIG_NUM_IRQ_PRIO_BITS)
__Vendor_SysTickConfig (set to 0 - standard SysTick)
Jira: ZEP-1568
Change-Id: Ibc203de79f4697b14849b69c0e8c5c43677b5c6e
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
ARM's Cortex-M Prototyping System (or MPS2) [1] is a board containing
devices such as RAM, ethernet and display, and at its heart there is an
FPGA which can be programmed with various 'SoCs' which implement the
CPU, SRAM, UARTs, SPI, DMA, etc. There are also software simulations of
systems based on this hardware which are part of ARM's Fixed Virtual
Platforms (FVPs).
All of the above could be regarded SoCs in the same series so we will
treat them as such in Zephyr.
In this initial patch we add SoC support for the public FPGA image
which implements a Cortex-M3 CPU, and includes definitions to support
use of the UARTs on this.
ARM's documentation for MPS2 images are titled 'Application Note ANnnn'
where the number nnn is different for each 'SoC'. E.g. Application Note
AN385 is for "ARM Cortex-M3 SMM on V2M-MPS2" [2]. The files ARM supply
for programming the board firmware also make extensive use of the ANnnn
nomenclature, so we will use this for the SoC name in Zephyr. E.g. the
Cortex-M3 SoC will be called 'mps2_an385'. Note, it is not possible to
use the CPU type (e.g. M3) for the name as there are multiple FPGA
images for some CPU types (e.g. there are three Cortex M7 images
with differing FPU and MPU support).
[1] https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php
[2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0385c/index.html
Change-Id: Ice54f2d2cde7669582337f256c878526139daedd
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Now that we have a more generic mcux spi driver that can be used across
multiple Kinetis SoCs, remove the specific k64 spi driver.
Jira: ZEP-1374
Change-Id: Ifc324374f305837f5e3d2cfd7ad30d3608865b5b
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Kumar Gala