Split ARM and ARM64 architectures.
Details:
- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
(arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
boards/bcm_vk/viper directory
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Commit 0a7b65e tweaked the CREATE_OBJ_LEVEL macro in such a way
that it would break the expected sorting order.
For example if you had 2, 19, 20, 30 as the level, we'd end up sort
these to be 19, 2, 20, 30.
Fix this by adding aditional "_" symbol after the init level counter.
That allows to keep correct sort order (for both GNU and MWDT
toolchains) and distinguish init level counter from section suffix
(for MWDT toolchain).
Fixes zephyrproject-rtos#33464
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
MWDT toolchain adds additional suffix to sections name
in case of ffunction-sections / fdata-sections are enabled.
Let's pick a single set of rules and syntax that work.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
New macro GROUP_ROM_LINK_IN for text/rodata sections
New macro GROUP_NOLOAD_LINK_IN for bss/noinit sections
GROUP_FOLLOWS_AT is unused anywhere in the kernel for
years now and has been removed.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Since linker_final_pass.cmd is the actual linker script being
used to link the final Zephyr binary, rename it to linker.cmd.
This also renames LINKER_PASS2 to LINKER_ZEPHYR_FINAL simply
to clarify what it is used for, instead of ambiguous pass #n.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Using this actually would result in a linker input section being
put between output sections which is not correct syntax.
We have never seen this simply because the generated ones would
be included instead of the in-tree ones. So remove this just in
case, instead of linker errors.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There's no need to duplicate the linker section for each architecture.
Instead, move the section declaration to common-rom.ld.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Adds a Proxy callback structure with a callback for Node ID enable and
disable. This API follows the Friend and LPN API pattern in mesh/main.h,
and can be expanded with more callbacks later.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
We need to do a few things differently if we are to support
a virtual memory map, i.e. CONFIG_MMU where CONFIG_KERNEL_VM_BASE
is not the same as CONFIG_SRAM_BASE_ADDRESS.
- All sections must be specified with a VMA and LMA, where
VMA is the virtual address and LMA is the physical memory
location.
- All sections must be specified with ALIGN_WITH_INPUT to
keep VMAs and LMAs synchronized
To do this, the existing linker macros need some adjustment:
- GROUP_LINK_IN undefined when CONFIG_KERNEL_VM_BASE is not
the same as CONFIG_SRAM_BASE_ADDRESS.
- New macro GROUP_ROM_LINK_IN for text/rodata sections
- New macro GROUP_NOLOAD_LINK_IN for bss/noinit sections
- Implicit ALIGN_WITH_INPUT for all sections
GROUP_FOLLOWS_AT is unused anywhere in the kernel for years
now and has been removed.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
__tbss_start should be a virtual address.
__tdata_start should also be a virtual address, unless we're
using XIP in which case each thread should copy its thread-
local data out of flash.
Fixes issues with a kernel linked at a virtual address.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Following the idiom used for system calls, add script support to read
the initial application binary to identify which devices are defined,
and to use their offset in the device array as their unique handle
rather than the externally-defined ordinal from devicetree. The
device dependency arrays are updated to use these handles.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Move the busy status from a global atomic bit sequence to atomic flags
in the device PM state. While this temporarily adds 4 bytes to each
PM structure the whole device PM infrastructure will be refactored and
it's likely the extra memory can be recovered.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Separate the state indicator of whether the initialization function
has been invoked from the success or failure of the initialization.
This allows precise confirmation that the device is ready (i.e. it has
been initialized, and that initialization succeeded).
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add support for backup SRAM initialization found in multiple STM32
microcontrollers. Linker script facilities are also provided to make it
easy to define variables in the backup SRAM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
In binutils SORT is an alias for SORT_BY_NAME. Don't confuse people
by replacing explicit use of the actual directive with an alias for
that same directive.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The CONFIG_KERNEL_COHERENCE framework merged with a typo that left its
validation asserts disabled. But it was written before the "kernel
stacks" feature merged, and so missed the K_KERNEL_STACK_* macros,
which need to put their stacks into __stackmem and not merely
__noinit.
Turning the asserts on exposed the bug.
Fixes#32112
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This lets the linker tell us what kind of alignment is required
for both tdata and tbss data when copying them into stack.
If they are not aligned as expected by the toolchain, generated
code would be accessing incorrect location for thread variables.
Fixes#32015
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The linker script defines `z_mapped_size` as follows:
```
z_mapped_size = z_mapped_end - z_mapped_start;
```
This is done with the belief that precomputed values at link time will
make the code smaller and faster.
On Aarch64, symbol values are relocated and loaded relative to the PC
as those are normally meant to be memory addresses.
Now if you have e.g. `CONFIG_SRAM_BASE_ADDRESS=0x2000000000` then
`z_mapped_size` might still have a reasonable value, say 0x59334.
But, when interpreted as an address, that's very very far from the PC
whose value is in the neighborhood of 0x2000000000. That overflows the
4GB relocation range:
```
kernel/libkernel.a(mmu.c.obj): in function `z_mem_manage_init':
kernel/mmu.c:527:(.text.z_mem_manage_init+0x1c):
relocation truncated to fit: R_AARCH64_ADR_PREL_PG_HI21
```
The solution is to define `Z_KERNEL_VIRT_SIZE` in terms of
`z_mapped_end - z_mapped_start` at the source code level. Given this
is used within loops that already start with `z_mapped_start` anyway,
the compiler is smart enough to combine the two occurrences and
dispense with a size counter, making the code effectively
slightly better for all while avoiding the Aarch64 relocation
overflow:
```
text data bss dec hex filename
1216 8 294936 296160 484e0 mmu.c.obj.arm64.before
1212 8 294936 296156 484dc mmu.c.obj.arm64.after
1110 8 9244 10362 287a mmu.c.obj.x86-64.before
1106 8 9244 10358 2876 mmu.c.obj.x86-64.after
```
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
XCC Clang doesn't emit load address when a section
is empty, resulting in __tdata_start not being
defined. So put a #ifdef guard for the thread local
storage linker script to avoid this issue.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Both _IRQ_VECTOR_TABLE_SECTION_NAME and _SW_ISR_TABLE_SECTION_NAME
are defined with asterisk at the end in an attempt to include
all related symbols in the linker script. However, these two
macros are also being used in the source code to specify
the destination sections for variables. Asterisks in the name
results in older GCC (4.x) complaining about those asterisks.
So create new macros for use in linker script, and keep
the names asterisk free.
Fixes#29936
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Page tables created at build time may not include the
gperf data at the very end of RAM. Ensure this is mapped
properly at runtime to work around this.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are needed on MMU systems and define where the kernel
image resides in virtual memory at boot so that it may be
memory-mapped.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
MWDT toolchain adds additional suffix to sections name in case of
ffunction-sections / fdata-sections are enabled.
The 40d3653758 commit
(device: add post-process of elf file to manage device handles)
breaks linkage with MWDT toolchain as it adds new sections
which are not meet MWDT requirements.
Let's pick a single set of rules and syntax that work for all
toolchain.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Page tables created at build time may not include the
gperf data at the very end of RAM. Ensure this is mapped
properly at runtime to work around this.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are needed on MMU systems and define where the kernel
image resides in virtual memory at boot so that it may be
memory-mapped.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Following the idiom used for system calls, add script support to read
the initial application binary to identify which devices are defined,
and to use their offset in the device array as their unique handle
rather than the externally-defined ordinal from devicetree. The
device dependency arrays are updated to use these handles.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This adds a somewhat special purpose IPC mechanism. It's intended for
applications which have a "work queue" like architecture of discrete
callback items, but which need the ability to schedule those items
independently in separate threads across multiple CPUs. So P4 Work
items:
1. Can run at any Zephyr scheduler priority and with any deadline
(this feature assumes EDF scheduling is enabled)
2. Can be submitted at any time and from any context, including being
resubmitted from within their own handler.
3. Will preempt any lower priority work as soon as they are runnable,
according to the standard rules of Zephyr priority scheduling.
4. Run from a pool of worker threads that can be allocated efficiently
(i.e. you need as many as the number of CPUs plus the number of
preempted in-progress items, but no more).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Adds a linker section for Cortex-M instruction tightly coupled memory
(ITCM), similar to the existing section for DTCM. A new executable MPU
region is not added as there isn't currently a need to make this section
accessible to user mode. This section can be enabled by setting a device
tree chosen node zephyr,itcm.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
- Remove SYS_ prefix
- shorten POWER_MANAGEMENT to just PM
- DEVICE_POWER_MANAGEMENT -> PM_DEVICE
and use PM_ as the prefix for all PM related Kconfigs
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The linker section for emulators (emulation drivers) is
incorrectly named "log_const_sections" possibly due to
simply copy-and-paste error. This section has nothing to
do with logging, so rename the emulators section.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit adds a new driver category for memory controller
peripherals. There is no API involved for now, as it has not been found
necessary for first implementation.
STM32 Flexible Memory Controller (FMC) is the only controller supported
for now. This peripheral allows to access multiple types of external
memories, e.g. SDRAM, NAND, NOR Flash...
The initial implementation adds support for the SDRAM controller only.
The HAL API is used, so the implementation should be portable to other
STM32 series. It has only been tested on H7 series, so for now it can
only be enabled when working on H7.
Linker facilities have also been added in order to allow applications to
easily define a variable in SDRAM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
There are x86 platforms where the IRQ configuration register for PCIe
is not pre-populated and the OS needs to assign a number dynamically
by writing to the register.
In order to allocate interrupts we have to know which ones have been
hard-coded in device tree. We accomplish this by collecting these
values through the IRQ_CONNECT() macro and placing them in a dedicated
linker section (in ROM).
The full set of allocated interrupts are managed through a bitmap, and
the pre-allocated values (from the linker section) are inserted into
this upon initial runtime access.
This patch introduces a new pcie_alloc_irq() API that drivers can use
to allocate interrupt line numbers. The two in-tree drivers that were
using this API (I2C and UART) are converted to use the new API.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
GCC and binutils support for the SPARC architecture.
Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com>
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This change adds support for DNS Service Discovery (DNS-SD)
as described in RFC 6763.
Fixes#29099
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Encapsulates the Heartbeat state and functionality in a separate
heartbeat module, removing all manipulation of the heartbeat state from
the transport and config server modules.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
This adds the tdata and tbss sections required for thread local
storage. They are in ROM area as these sections are not to be
directly accessed, but copied to thread local storage area at
thread creation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add Queue Size and Receive Window information to lpn
callback function to notify upper layer to determine
currently friend node information, which may be used
in future.
Add Callback structure to notification application which friendship
has been changed.
Add function `bt_mesh_friend_terminate` let's app layer determine
terminate friendship manually.
Signed-off-by: Lingao Meng <mengabc1086@gmail.com>
This is a major refactoring of the handling of the cryptographic
material of both the network and transport layers. The aim is to
encapsulate the key object manipulation, and improve overall modularity.
Pulls Applications and Subnets out of the bt_mesh and into separate
modules, with static storage types on the data. This has several
side-effects:
- The Config Server no longer operates directly on the bt_mesh.subs and
bt_mesh.apps lists, but goes through a public configuration interface,
following the pattern set in #27908.
- All iteration through the keys is done through iteration APIs
- Key resolution on RX and TX is centralized.
- Changes to the keys triggers events the other modules can register
handlers for.
- Friendship credentials are stored in the lpn and friend structures.
Part of #27842.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
Zephyr SMP kernels need to be able to run on architectures with
incoherent caches. Naive implementation of synchronization on such
architectures requires extensive cache flushing (e.g. flush+invalidate
everything on every spin lock operation, flush on every unlock!) and
is a performance problem.
Instead, many of these systems will have access to separate "coherent"
(usually uncached) and "incoherent" regions of memory. Where this is
available, place all writable data sections by default into the
coherent region. An "__incoherent" attribute flag is defined for data
regions that are known to be CPU-local and which should use the cache.
By default, this is used for stack memory.
Stack memory will be incoherent by default, as by definition it is
local to its current thread. This requires special cache management
on context switch, so an arch API has been added for that.
Also, when enabled, add assertions to strategic places to ensure that
shared kernel data is indeed coherent. We check thread objects, the
_kernel struct, waitq's, timeouts and spinlocks. In practice almost
all kernel synchronization is built on top of these structures, and
any shared data structs will contain at least one of them.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is data and needs the implicit ALIGN_WITH_INPUT that
is provided with SECTION_DATA_PROLOGUE. Otherwise misalignment
may occur if XIP is turned on.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This uses the new macros so the common kernel objects can be
garbage collected if they are not referred directly anywhere
in the code. This is useful for reducing library data size
as not all library functions and their corresponding kobjects
are being used.
Fixes#20663
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The iterable section macros Z_ITERABLE_SECTION_ROM()/_RAM() uses
Z_LINK_ITERABLE() which does KEEP() on all symbols. This results
in all symbols under those sections being kept in final image
even though these symbols are not referred directly from the code.
This adds the new set of macros which does not force KEEP() on
the symbols, and allows symbols to be garbage collected.
The existing macros are kept as-is so as not to change their
behaviors.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Align multiline string definition syntax in ASSERT in linker
script. This allows to use linker script with ASSERT provided
by linker (i.e GNU toolchain) or dummy ASSERT defined as
preprocessor macros (ARC MWDT toolchain).
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
MWDT toolchain adds additional suffix to sections name in case of
ffunction-sections / fdata-sections are enabled.
As proposed by Andy Ross let's pick a single set of rules
and syntax that work.
Suggested-by: Andy Ross <andy@plausible.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Carlo Caione