zephyr

Commit Graph

Author	SHA1	Message	Date
Kumar Gala	ccad5bf3e3	drivers: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>	2017-04-21 10:06:48 -05:00
Jean-Paul Etienne	d7b713e5b8	interrupt_controller: added support for the SiFive Freedom E310 PLIC driver The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows the riscv PLIC specification as defined in the riscv privilege architecture specification. It provides implementation for the riscv PLIC APIs as required by the riscv-privilege SOC Family for SOCs providing support for the RISCV_HAS_PLIC config. Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>	2017-04-02 15:15:16 +00:00

Author

SHA1

Message

Date

Kumar Gala

ccad5bf3e3

drivers: convert to using newly introduced integer sized types

Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.

Jira: ZEP-2051

Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

2017-04-21 10:06:48 -05:00

Jean-Paul Etienne

d7b713e5b8

interrupt_controller: added support for the SiFive Freedom E310 PLIC driver

The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows
the riscv PLIC specification as defined in the riscv privilege
architecture specification.

It provides implementation for the riscv PLIC APIs as
required by the riscv-privilege SOC Family for SOCs providing
support for the RISCV_HAS_PLIC config.

Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>

2017-04-02 15:15:16 +00:00

2 Commits