Commit Graph

8 Commits

Author SHA1 Message Date
Ulf Magnusson bd6e04411e kconfig: Clean up header comments and make them consistent
Use this short header style in all Kconfig files:

    # <description>

    # <copyright>
    # <license>

    ...

Also change all <description>s from

    # Kconfig[.extension] - Foo-related options

to just

    # Foo-related options

It's clear enough that it's about Kconfig.

The <description> cleanup was done with this command, along with some
manual cleanup (big letter at the start, etc.)

    git ls-files '*Kconfig*' | \
        xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /'

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-04 17:31:27 -05:00
Charles E. Youse 200056df2f arch/x86: rename CONFIG_X86_MULTIBOOT and related to CONFIG_MULTIBOOT
Simple naming change, since MULTIBOOT is clear enough by itself and
"namespacing" it to X86 is unnecessary and/or inappropriate.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-29 12:30:34 -07:00
Charles E. Youse 34120b9ee5 boards/x86/gpmrb: disable Multiboot header generation
We don't require this to boot with SBL, so disable for now.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-21 16:43:26 -07:00
Charles E. Youse 3bc79fdf2c arch/x86: refactor APIC timer configuration to SoC level
The APIC is part of the SoC, not the board, so move the defaults down.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-21 16:43:26 -07:00
Andrew Boie 9df9994572 x86: fix XIP SOC support and defaults
XIP support in x86 was something of a mess. This
patch does the following:

- Generic ia32 SOC no longer defines a "flash" region
  as generic X86 devices don't have a microcontroller-
  like concept of flash. The same has been done for apollo_lake.
- Generic ia32 and apollo_lake SOCs starts memory at 1MB.
- Generic ia32 SOC may optionally have CONFIG_XIP enabled.
  The board definition must provide a flash region definition
  that gets exposed as DT_PHYS_LOAD_ADDR.
- Fixed definitions for RAM/ROM source addresses in ia32's
  linker.ld when XIP is turned off.
- Support for enabling XIP on apollo_lake SOC removed, there's
  no use-case.
- acrn and gpmrb boards have flash and XIP related definitions
  removed.
- qemu_x86 has a fake flash region added, immediately after system
  RAM, for use when XIP is enabled. This used to be in the ia32 SOC.
  However, the default for qemu_x86 is to now have XIP disabled.
- Fixed tests/kernel/xip to run by default on boards that enable
  XIP by default, plus an additional test to exercise XIP on
  qemu_x86 (which supports it but has XIP switched off by default)

The overall effect of this patch is to:

- Remove XIP configuration for SOC/boards where it does not make
  any sense to have it
- Support testing XIP on qemu_x86 via tests/kernel/xip, but leave
  it off by default for other tests, to ensure it doesn't bit-rot
  and that the system works in both scenarios.
- XIP remains an available feature for boards that need it.

Fixes: #18956

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-11 21:11:38 -04:00
Carles Cufi afcbc9992c doc: Use west everywhere to build and flash
Instead of having a mix of west and CMake/ninja instructions for
building and flashing, document it using only west. This will help
clarify that west is the default build tool in Zephyr and should also
reduce confusion over what tool to use.
Note that the biggest change is changing the default in
doc/extensions/zephyr/application.py for :tool:, from all to west.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2019-08-27 19:36:24 +02:00
David B. Kinder 9bcf629828 doc: fix typo in gpmrb doc
Fix typo missed during regular review

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2019-06-05 21:13:33 -04:00
Charles E. Youse 69c01d11e5 boards/x86/gpmrb: add Gordon Peak MRB board
Add board support (and documentation) for the Intel Gordon Peak
Module Reference Board, a dev board based on the Apollo Lake SoC.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-04 14:50:47 -04:00