Don't busy-wait in uart_stm32_fifo_fill(), this routine is supposed
to be called on IRQ, and the waiting loop was shown to interfere
with interrupt-driven UART handling.
The original problem mentioned in the patch being reverted ("it is
possible to evaluate the TXE bit *before* H/W has had the
opportunity to detect that data is being processed") may still
exist and may require handling in a different way. The most obvious
way is to replace "while" loop with "if", because STM32 doesn't
have multi-level FIFO anyway. But I was dissuaded to include such a
change as part of this patch, so it's left for future analysis.
This reverts commit 49c2858d94.
Change-Id: Ib27b53ba3a29b84c1a2dccff6d33f4118680cc19
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix doxygen comment typos used to generate API docs
Change-Id: I6fd5051c99bdcc731740c92001e525349c254d85
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Added serial (UART) driver for Atmel SAM MCU family.
Note:
- Error handling is not implemented
- The driver works only in polling mode, interrupt mode is
not implemented.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1959
Change-Id: I3e770fd1feb2ddf92cf405a9aa17be92eb32e19b
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add plumbing to build system and SoC level dtsi for the NRF52832 SoC.
We additionally add the necessary yaml files for the UART on the NRF52
SoCs.
Change-Id: I3b4a821b2993827e33d8e84bdbbc759d1521f8bd
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that all STM32 platforms are using device tree we can remove the
handling for !HAS_DTS from the serial driver.
Change-Id: Ifafc283f2509dd9a438f321e0b647720d4f13810
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that all NXP MCUX platforms are using device tree we can remove the
handling for !HAS_DTS from the serial drivers.
Change-Id: I05185142afa7fae83ce68de954202829868af88f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As part of the transition to Device Tree, a temporary
HAS_DTS configuration variable, and a .fixup file per board
with symbol aliases were added.
This patch removes the cc32xx related fixup file
definitions, except for those used additionally outside
the cc32xx drivers.
Since cc32xx has DTS files, and since HAS_DTS will always be true,
it also removes the 'if !HAS_DTS' blocks from the cc32xx Kconfig
files.
Change-Id: I1c1b9f734795f523342f82ab32f2a38983812c0b
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Previously, cc3200_launchxl board was not able to show the
Zephyr Boot Banner, as that required early initialization
of the UART driver, which was done POST_KERNEL.
This patch moves the pinmux and UART driver initialization
to PRE_KERNEL_1, allowing early printk, and the Boot Banner
to show.
Change-Id: I84a7c20c1d5bdc3de150dc6bb0adebc9a2d9f5cb
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Providing a new line, then an attribute on the same line as the
following closing bracket is odd. Move to something more
transitional and in line with regular coding standards.
Change-Id: I08f7cd76ca2f522a8b5b6de2e5baf94e95b5195a
Signed-off-by: Lee Jones <lee.jones@linaro.org>
It is possible to evaluate the TXE bit *before* H/W has had the
opportunity to detect that data is being processed. Therefore
we should hold off on any evaluation until TXE has initially been
set.
Change-Id: Iff26bfbe3ab419734003bf81a4cb357de83908e7
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Currently the entries for STM32 UART ports are at the same level than
the top menuconfig UART_STM32. As a result they are mixed with other
configs in the "Serial Drivers" menu.
Use if/endif grammar to put these entries under a dedicated STM32
submenu.
Change-Id: If28945204b801578d29f8cce7c2370ca3c2737a1
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Since all interrupts come in on the status line,
we only connect it for the KL2X.
Change-Id: Ia9e0d483fe68464a0eeab08c95a043260e5793b0
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
To secure correct signal levels on the pins by the UART when
the system is in OFF mode, the pins must be configured in
the GPIO peripheral as described in nRF5 Product
Specification.
UART Pin, Direction, Output Value:
RXD, Input, NA
CTS, Input, NA
RTS, Output, 1
TX, Output, 1
This commit sets the RTS line to a initial value of 1.
Change-id: I5147fe58033f42c979b9354798b6fd13d78f7f71
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
After activation of cube based driver support on L4 and F3 series,
this commits performs the clean up of F3 and L4 relative code to
native clock control drivers.
Indirectly, it makes pwm driver supported de facto on F3 series
Change-Id: Idac17103a9b5ef6eab540719343cc8f5865f15fa
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introducing STM32Cube based clock control driver for
stm32 family, update stm32 serial driver to support it.
Once supported across the whole family, a clean up will be done.
Change-Id: I7100bc699e7918c8be71d58091da1860ab734e25
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch adds the base DTS support for the KW41Z Freedom board. The
initial set of changes include SRAM, FLASH, IRQ controller and LPUART
support.
Change-Id: Ic68c4959ddad0c5cfe70d5576a0e58372b93ec9d
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
This patch adds DTS support to the ARM CMSDK UART driver. The DTS
currently specifies the IRQ, IRQ PRIO, and base address of the port.
Change-Id: I8e5bc81c013958be4297d563495bf126b53a83a9
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds device tree support to the STM32 UART driver. The base
address, interrupt, and interrupt priority values can now come from DTS.
Change-Id: I3c383da8b200037601ecb2dc087f99ef103761bb
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch ifdef's out information that would be redefined by
information generated from DTS. This patch also fixes up the serial
drives to work properly with the DTS generated information.
Change-Id: I912ccf35be23c107705a4866e5a68b3b51154ffa
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds DTS support and related files for the NXP Kinetis
platform. The DTS files contain the base definitions for the hardware
nodes on Kinetis platforms. The YAML files provide the definitions of
the contents of the DTS nodes.
The Kconfig changes were put in place to allow for the conversion of
existing drivers. Once those drivers are modified, the Kconfig options
that are replaced by the DTS information will be removed.
Change-Id: If110fffa99c0b12471cf2df206da6687277e4756
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit removes unnecessary CONFIG_SYS_POWER_DEEP_SLEEP protection
in shim drivers as QMSI 1.4 has introduced empty context save/restore
functions that can be called in Quark D2000, therefore keeping common
code at the shim driver level for Quark SE and D2000.
Change-Id: Ia2a466327f999668c6511c0193014e9151bff6ae
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
Added basic USART driver for Atmel SAM MCU family. USART is a very
comprehensive module, currently only basic features sufficient to
support printf functionality are implemented by this driver.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Ia9710e4069243fb6c30de45953dfc1fe1266b63a
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Adds a shim layer around the mcux lpuart driver to adapt it to the Zephyr
serial interface.
NXP has multiple uart hardware blocks that implement different features
and have different register maps. The k64 has a uart block called
'uart', while the kw41 has a uart block called 'lpuart' (low power
uart). The MCUXpresso SDK provides separate drivers for each type of
uart block but with similar software interfaces. As a result, there are
also separate shim drivers in Zephyr. There is a 1:1:1 relationship
between hardware block, mcux driver, and mcux shim driver.
Because we now have two mcux shim drivers for the uart interface, a new
naming convention is created:
<interface>_mcux_<hw block>
Where <interface> is the name of the Zephyr interface, in this case
'uart'. This convention is not new.
<hw block> is the name of the NXP hardware block, in this case 'lpuart'.
This is the new part, and distinguishes different hardware blocks
for the same interface.
Change-Id: I3a80b9bffa116bbb2b02ee950d4bdd79a19a4edc
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The NXP copyright should not have 'Semiconductors, Inc' in it.
Change-Id: I6e290146d49bf22d1d40b7fa764bb53b6b122303
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Now that we have a more generic mcux serial driver, remove the uart_k20
driver.
Jira: ZEP-719
Change-Id: I51a3237454140feabbfe18ac2c8ee451e572c7be
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a shim layer around the mcux uart driver to adapt it to the Zephyr
serial interface. Unlike the existing (and confusingly-named) uart_k20
driver, this driver can be used for k64 and other Kinetis SoCs.
Implements polling and interrupt-driven serial interface functions that
are logically equivalent to the uart_k20 driver. Adds an extra instance,
irq_tx_empty(), and err_check() that aren't implemented in the uart_k20
driver.
Jira: ZEP-719
Change-Id: Iab99542e7ec921ef4f361437768113fee01e5fe8
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
riscv-qemu UART:
1) comprises only one register that is used to send or
receive characters in a polling fashion.
2) does not have a FIFO and is not interrupt-driven.
Change-Id: I9408f1776eba4cec4aa203a5da759ec04bcddf1f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
UART 16750 is basically a UART 16550 with a 64-bytes FIFO.
The 64-bytes FIFO can be enabled via register FCR.
Account for it in the uart_ns16550 driver whenever the
CONFIG_UART_NS16750 variable is set.
Change-Id: I2342b28a41d03c96410bbfbe57e4b5a4e335731d
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This patch adds the ARG_UNUSED macros to some function
arguments to avoid compiler warnings.
Change-Id: I628aea55d98cf8519c046ae5835e95cfa70a973f
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
To make way for the upcoming blinky and GPIO support for nRF5x-based
boards, this change addresses the hardcoded dependencies in Kconfig
default configurations of the different boards, moving the common option
defaults to the SoC default configuration itself.
Change-Id: I8db0750311ad5a12b76237b39438376f20f6f496
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The new Nordic MDK redefines certain UART signal names for backwards
compatibility with the new nRF52840 IC.
This patch addresses the potential name conflict between the redefined
signals and the existing variable names defined in the UART driver.
JIRA: ZEP-1418
Change-Id: I559d9335d2eeaa0a88d3f261b70508a1c98b989d
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This patch enables the clock control interface into the ARM LTD
CMSDK APB UART driver.
Jira: ZEP-1300
Change-Id: Ic0a214beb02d56ffb02ad4e6ca26b80805c0a4e6
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Deal with STM32L4X additions for clock and interrupt handling to the
uart driver.
Change-Id: I6e8dafb132dafea54b8f31a3a5cb6e35a207574d
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There was a misalignment between Zephyr UART device numbering and
SoC UART IP. Device "UART_1" was mapped to IP USART_2, which could
be confusing for user.
This commit allows to align "UART_1" to IP USART_1.
Change is propagated to all STM32F103RB/STM32F401RE based boards and
respective pinmux drivers
Change-Id: Ia8099dfeec7b9c0c686c2a58ccb4dbb1a55b6537
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32Cube based implementation allows single driver file for
all stm32 based SoCs.
By maximizing code reuse, use of STM32Cube eases new SoCs
porting into Zephyr and provides better maintanability and
maturity.
Change-Id: Ief4b723add3dfc8b2a839683559c5a4c5d5eb837
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit replaces the nanokernel.h include by kernel.h.
Change-Id: Ib42fbf2d9f77a73c0831f569b3dbbfb342ea2e1d
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
Add driver for CMSDK APB UART ports. The driver implements RX and TX
functionalities. Data transmission is implemented using polling and
interrupts. The driver default configuration for the port is to use
8bit data transmission, 1 stop bit, no parity control.
The driver exposes a public uart driver API and allows to register up
to five UART devices: from 'UART_0' to 'UART_4'. The driver performs
the required pinmux, the clock control configuration is left to the
platform.
The driver has been verified to work with the Hello World sample
application on a Beetle Board.
Jira: ZEP-1245
Change-Id: I5baf78b7659aae2a574d8e66205e6fd5eb579133
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The uart_k20 serial driver incorrectly assumed that all instances of the
UART peripheral are driven by the system clock, when actually some
instances are driven by the bus clock (which usually runs at half the
system clock). This caused incorrect baud rate calculations for UART
instances driven by the bus clock (UART2-4).
Change-Id: I38041781cdee146912bb5167e7c71d6416b966b5
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The pinmux configuration is done during board initialization.
This was validated using the following Zephyr apps:
- samples/hello_world
- samples/philosophers
- samples/drivers/uart
- samples/shell
UARTA0 is currently supported.
Change-Id: I85727c622d4d42183cc9f2f8b43d653e245dd17e
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Remove the Zephyr implementation and
update the uart_qmsi driver to use new QMSI PM APIs.
Jira: ZEP-998
Change-Id: I418e6384c16e374e9062820e12648a2d524a312d
Signed-off-by: JuanX Solano Menacho <juanx.solano.menacho@intel.com>
Use the macros provided by QMSI (or by ourselves, when QMSI doesn't
have them yet) to register interrupts independently of which core it's
building for.
Change-Id: I83fd7e42598b45aef8132316906a3bff291dfe92
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Paul Sokolovsky