Commit Graph

415 Commits

Author SHA1 Message Date
Gerard Marull-Paretas 88a69674c0 drivers: use new PM macros
Port some drivers to the recently introduced macros to showcase its
usage and be able to do some initial testing (nRF52840).

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-19 10:11:32 +01:00
Gerard Marull-Paretas c78c312c82 drivers: interrupt_controller: i/loapic: use DEVICE_DEFINE
Define the device using DEVICE_DEFINE macro, so that a single option can
be used regardless of PM being enabled or not.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-19 10:11:32 +01:00
Gerard Marull-Paretas 4baf1e01ff drivers: use common PM action callback naming
The PM callback is no longer referenced as "pm_control" but
"pm_action_cb", so reflect this new naming on the callbacks.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-03 20:27:18 -04:00
Jay Vasanth c214c59548 Microchip: MEC172x: eSPI driver
MEC172x eSPI driver, eSPI pin programming, interrupt updates related
to eSPI and other updates for MEC172x eSPI driver.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2021-10-26 09:27:20 -04:00
Neil Armstrong 71766f5c05 interrupt_controller: gicv3_its: Implement Indirect Two-level table
When the ITS is configured with a large number of DeviceID bits,
up to 32, the Device Translation Table can be configured as
"indirect" mode consisting of a 2-level table with the first
level entries pointing to a second level table for each
group of DeviceIDs.

This is necessary to support platforms with DeviceID bits > 16.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-21 10:56:15 -04:00
Tim Lin 41c9b71450 ITE: soc: add cpu idle task
Implement the CPU idle task. The system should enter this task when
there is no any task to ensure power saving.

Tested on it8xxx2_evb board. It will reduce 12.5mA when system enters
the CPU idle task.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-10-08 13:01:06 +02:00
Daniel Leung ed83474b10 interrupt_controller: remove CONFIG_DW_ICTL_OFFSET
This kconfig is only used for one board and is simply an alias
to another kconfig. So remove CONFIG_DW_ICTL_OFFSET and apply
the value directly to the other kconfig.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-10-06 19:43:48 -04:00
Evgeniy Paltsev 6807e02655 ARC: IRQ: drop excessive PM_DEVICE hooks
All ARC CPUs (supported by Zephyr) don't lose core interrupt
controller configuration after switching to sleep mode / modes,
so we don't need to save & restore it's configuration with PM.

This PM code most likely was added for Arduino 101 (Genuino 101)
board which isn't supported by Zephyr anymore - so we can drop
it.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
2021-10-05 07:48:47 -04:00
Evgeniy Paltsev e1455fafdf ARC: IRQ: drop unused _VectorTable declaration
We don't use '_VectorTable' in the driver, so let's drop it's
declaration.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
2021-10-05 07:48:47 -04:00
Felipe Neves 949a6a8e53 interrupt-controller: intc_esp32c3: make logs optional
Allowing cleaner debug experience and preventing unwanted
outputs during debug.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-10-02 14:33:24 -04:00
Felipe Neves b97c2da2f2 interrupt_controller: intc_esp32c3: added intc driver
For esp32c3 and replaces the hardcoded interrupt
attaching procedures with this new driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-10-02 14:33:24 -04:00
Neil Armstrong a737999b5b interrupt_controller: gicv3: add Interrupt Translation Service support
This implements support for the optional Interrupt Translation Service
(ITS) module of the GICv3 Interrupt Controller.

The current implementation is designed for MSI/MSI-X interrupt delivery
in mind.
The gicv3 driver calls each ITS INVALL command when LPI interrupts are
enabled/disabled.
A simple atomic integer is used to allocate unique LPI INTIDs to ITS
users.
CPUs numbers are directly mapped as ICIDs into the Collections Table.

As a limitation it doesn't support indirect Device table to simplify
implementation but may use a large amount of memory.

INV, DISCARD, MOVI and MOVALL commands are not implemented.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-09-28 19:45:29 -04:00
Neil Armstrong e819bd8f34 interrupt_controller: gicv3: add support for LPIs
The LPI (Locality-specific Peripheral Interrupts) are edge-triggered
message-based interrupts that can use an Interrupt Translation
Service (ITS) to route an interrupt to a specific Redistributor and
connected PE.

This implement the necessary LPI support when an ITS is enabled.

The LPI states are stored in memory-backed tables.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-09-28 19:45:29 -04:00
Dino Li 29d039335f cleanup: soc: it8xxx2: remove unnecessary code
Code removed:
- IT8XXX2 doesn't support soc level software interrupt hence remove
  them.
- To use common macro to access csr (control status register).
- To remove CONFIG_RISCV_HAS_PLIC related code. IT8XXX2 uses its own
  interrupt controller code.
- To remove ite_write and ite_read. We don't use them anymore.

Code changed:
- Return true from arch_irq_is_enabled() when external interrupt-enable
  bit, and SOC's IER are both true.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-09-28 11:36:23 +02:00
Jiafei Pan 6f1dc5d3a9 drivers: gicv3: set SPI's affinity when it is enabled
When affinity routing is enabled for Non-secure state
( GICD_CTLR.ARE_NS is '1'), need to set routing information
for the SPI interrupt.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2021-09-07 11:31:22 -04:00
Torsten Rasmussen e1481fee4a drives: cmake: zephyr_library_property(ALLOW_EMPTY TRUE) on drivers lib
This commit now sets the Zephyr library property `ALLOW_EMPTY` to
silence the warning:
`No SOURCES given to Zephyr library: drivers__interrupt_controller`

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-09-07 11:42:47 +02:00
Glauber Maroto Ferreira 489c012198 esp32: drivers: interrupt_controller: make it common for xtensa socs
by including interrupt allocation feature whenever an Xtensa-based
Espressif SoC is selected.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-08-27 17:34:41 -04:00
Glauber Maroto Ferreira 2c031caed0 esp32s2: drivers: interrupt_controller: add interrupt allocation support
through the reuse of current esp32 interrupt allocator.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-08-27 17:34:41 -04:00
Henrik Brix Andersen a2791ccfef drivers: interrupt_controller: plic is independent of risc-v privileged
The RISC-V Platform-Level Interrupt Controller (PLIC) was moved from the
RISC-V Privileged Specification v1.11 to a separate specification
(see https://github.com/riscv/riscv-plic-spec).

Reflect this by not automatically enabling the PLIC interrupt controller
driver for all RISC-V privileged SoCs, but only for SoCs with the
CONFIG_RISCV_HAS_PLIC Kconfig option enabled.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-25 18:06:34 -04:00
Daniel Leung 9fa5437447 drivers: interrupt_controller: build as static library
Instead of putting object files inside libzephyr.a,
simply build a separate static library as most other
driver types are doing this already.

Also sort the entries alphabetically.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-08-17 06:06:03 -04:00
Gerard Marull-Paretas 7ccc1a41bc pm: use actions for device PM control
Instead of passing target states, use actions for device PM control.
Actions represent better the meaning of the callback argument.
Furthermore, they are more future proof as they can be suitable for
other PM actions that have no direct mapping to a state. If we compare
with Linux, we could have a multi-stage suspend/resume. Such scenario
would not have a good mapping when using target states.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas 6d273f49bd pm: fix incorrect usages of PM_DEVICE_STATE_OFF
According to the documentation the OFF state has to be used when the
devices is fully turned off, ie, power removed. Most drivers were using
a sort of fall-through for all non-active states, leading to behaviors
not following the specifications.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas 495672ab62 pm: cleanup pm control callback implementations
- Return -ENOTSUP if the requested state is not supported
- Remove redundant "noop style" functions.
- Use switch everywhere to handle requested state (not necessary in all
  drivers, but better take off with consistency in place after current
  changes).

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas d41dadc569 pm: rename PM_DEVICE_STATE_SUSPEND to PM_DEVICE_STATE_SUSPENDED
The verb tense for the suspended state was not consistent with other
states. The likely reason: state was being used as a command/action.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas 56a35e5682 pm: converge to suspend state for low power modes
The difference between low power and suspend states is a thin blur line
that is is not clear and most drivers have used indistinctly. This patch
converges to the usage of the suspend state for low power, since
contrary to the low power state, it is used by both system and runtime
device PM. The low power state is still kept, but its future is unclear
and needs some discussion.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas c6cce80ac4 pm: remove incorrect usages of force suspend
Some devices are using PM_DEVICE_STATE_FORCE_SUSPEND as a sort of low
power state, something that is not correct. In fact, this state is not
an actual state and will be eventually moved, if found necessary, to an
action or command.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas 920f30cc0e pm: simplify state change check logic
The device PM control function will only be called if the requested
state is different from the current one. A significant amount of drivers
were checking for state changes, now unnecessary. This patch removes all
this redundant logic.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas 11eef4d8c8 pm: device: remove pointer usage for state
Since the state is no longer modified by the device PM callback, just
use the state value.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas 9e7d545bb4 pm: device: remove ctrl_command callback argument
The ctrl_command is not used anymore, so remove it from the callback
signature.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas da0ff4ae46 pm: device: remove usage of ctrl_command
The callback is now invoked to set the device PM state in all cases, so
the usage of ctrl_command is redundant.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas c2cf1ad203 pm: device: remove usage of local states
The device PM subsystem already holds the device state, so there is no
need to keep duplicates inside the device. The pm_device_state_get has
been refactored to just return the device state. Note that this is still
not safe, but the same applied to the previous implementation. This
problem will be addressed later.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Erwan Gouriou 06b94f20aa drivers: gpio & interrupt_controller: Add stm32 u5 support
Add changes to STM32 GPIO and Interrupt controller driver
to support stm32u5 series.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-07-29 07:28:32 -05:00
Scott Worley 6b3749d2ff Microchip: MEC172x Add aggregated interrupt driver
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-26 12:24:52 -04:00
Ruibin Chang 78ef5ace6a ITE drivers/intc_ite_it8xxx2: correct logic operation
Interrupt polarity register don't support rising and
falling edge triggered at the same time, so I correct
logic operation to match this.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-07-24 21:26:49 -04:00
Sylvio Alves e01f18441e intr: esp32: conf log default level
Only enable interrupt allocator logs if config is set

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-07-20 20:01:47 -04:00
Dino Li ce7c7bb5f9 it8xxx2: intc: protect interrupt enable registers of soc
Because these two functions are called from threads and ISR.
And they run a bit-wise OR operation on the interrupt registers.
So protect them to prevent race condition between thread and ISR
context where causing an interrupt won't enable as expected.

eg.
- Pseudo code of thread enable IER1's bit1:
1. load word from IER1 (0x40) and write into CPU register S1
   => S1=0x40
2. Or S1's bit1
   => S1=0x42
(But if an interrupt is triggered here)
3. Store word to IER1 from S1
   => IER1=0x42
(IER1 will be 0x42 not 0x43, IER1's bit0 is disable again due to the
race condition above)

-Pseudo code of ISR enable IER1's bit0
1. load word from IER1 (0x40) write into CPU register S2
   => S2=0x40
2. Or S2's bit0
   => S2=0x41
3. Store word to IER1 from S2
   => IER1=0x41
4. Go back to thread.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-20 20:00:39 -04:00
Glauber Maroto Ferreira 9ae5fd1b34 esp32: drivers: interrupt_controller: add interrupt allocation support
Add interrupt allocation support for ESP32.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-07-16 07:19:28 -04:00
Dino Li 7d5411d6e0 soc: it8xxx2: introduce SOC_IT8XXX2_PLL_FLASH_48M option
Enable SOC_IT8XXX2_PLL_FLASH_48M at default to reduce latency of
fetching code from flash.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-13 09:44:29 -04:00
Gerard Marull-Paretas 26ad8376bd pm: remove callback from control function
The callback is not used anymore, so just delete it from the pm_control
callback signature.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-07-13 09:36:45 -04:00
Gerard Marull-Paretas 217e610d8f pm: remove redundant callback usage
the device PM callback is not used anymore by the device PM subsystem,
so remove it from all drivers/tests using it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-07-13 09:36:45 -04:00
Flavio Ceolin db9756045e drivers: intc_arcv2_irq_unit: Fix arc_v2_irq_unit_device_ctrl
Fix some leftovers from the pm_device_state changes.

Fixes build problem introduced in
cc2f0e9c08.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-07-09 12:51:36 -05:00
Dino Li cb307e2c64 driver: intc: it8xxx2: wait until two equal interrupt values are read
This change ensures the CPU won't get an interrupt number which is
being generated.

it8xxx2 has a limitation for interrupt vector register.
CPU may read incorrect interrupt number in ISR.

The following is an example that got incorrect interrupt number:
1. Register IVECT = 0x10. (no interrupt pending/IVECT_OFFSET_WITH_IRQ)
2. Chip INT6 interrupt occurs (IVECT = 0x16) and jump to ISR.
3. Read interrupt vector register to determine interrupt number.
4. Higher priority interrupt occurs (for example: INT158, IVECT = 0xAE)
while the CPU is reading the interrupt vector register for EC INT6,
CPU may end up with an incorrect interrupt number between 0x16 and 0xAE.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-09 12:45:01 -05:00
Gerard Marull-Paretas cc2f0e9c08 pm: use enum for device PM states
Move all PM_DEVICE_STATE_* definitions to an enum. The
PM_DEVICE_STATE_SET and PM_DEVICE_STATE_GET definitions have been kept
out of the enum since they do not represent any state. However, their
name has not been changed since they will be removed soon.

All drivers and tests have been adjusted accordingly.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-07-07 14:13:12 -04:00
Robert Szczepanski cf385b0a15 drivers: gpio_litex: add support for litex_vexriscv GPIO interrupts
This commit adds support for GPIO interrupts in GPIO driver for Litex
SoC Builder.

Signed-off-by: Robert Szczepanski <rszczepanski@internships.antmicro.com>
2021-06-04 16:24:52 -05:00
Mulin Chao a8a217f22d dts: npcx: replace series-prefix 'npcx7-' with famliy-prefix 'npcx-'
This CL replaces series-prefix "npcx7-" with family-"npcx-" for npcx dts
nodes such as 'espi-vws-map' and 'miwus-int-map'. Since we plan to
introduce the npcx9 and later series, adding a new node such as
npcx9-espi-vws-map for each series is more complicated and not
necessary.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-06-04 16:14:48 -05:00
Watson Zeng f05593e726 arc: interrupt_controller: increase irq unit priority
arc_v2_irq_unit_init function will init all interrupts and disable
they, we must make sure we call it first before we use interrupts.
so we need to increase its priority to highest in PRE_KERNEL_1 stage.

Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
2021-05-25 07:37:02 -05:00
Daniel Leung 1ad7349d17 intc: ioapic: mark data and functions as boot/pinned
This marks the data and functions into appropriate
linker sections.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-05-10 16:00:43 -05:00
Daniel Leung e4987484de intc: loapic: mark data and functions as boot/pinned
This marks the data and functions into appropriate
linker sections.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-05-10 16:00:43 -05:00
Daniel Leung 08d6386f3c intc: system_apic: mark functions as boot/pinned
This marks the functions into appropriate linker sections.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-05-10 16:00:43 -05:00
Flavio Ceolin 0c607adb63 pm: device: Align state names with system states
Change device pm states to the same pattern used by system power
management.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-05-07 18:35:12 -04:00