Commit Graph

14 Commits

Author SHA1 Message Date
Henrik Brix Andersen da2a0befbb drivers: can: unify CAN controller configuration in devicetree
Unify the CAN controller configuration done in Zephyr devicetrees:

- Specify a resynchronization jump width (sjw) of 1 time quanta in SoC
  devicetrees as this is the most common. Boards can override this if
  needed.
- Specify a sample point of 87.5% as recommended by CAN in Automation
  (CiA) in SoC devicetrees. Boards can override this if needed.
- Specify a bus speed of 125 kbits/second (arbitration phase) and 1
  Mbits/second (CAN-FD data phase) in board devicetrees as this is what
  is used by all Zephyr CAN samples.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-02-24 13:48:55 -08:00
Henrik Brix Andersen 2269408572 dts: bindings: can: remove #address-cells and #size-cells
Remove the requirement for specifying #address-cells and #size-cells
properties for CAN controller devicetree nodes.

CAN controllers do not have a common concept of devicetree child nodes
and thus have no need for these properties. This is in line with
upstream Linux kernel devicetree bindings.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-12-20 17:45:05 +01:00
Alexandre Bourdiol 7f3423ae48 dts: arm: st: stm32: move "st,prescaler" to timers instead of pwm
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-11-16 09:55:30 -06:00
Erwan Gouriou ea3b644c5d dts/arm/st: Default "st,prescaler" pwm property to 0
Property "st,prescaler" of binding "st,stm32-pwm" was set to 2
different default values 0 or 10000 in *.dtsi files.

Since this property rather depends on application than hardware
description, there is no reason to have 2 different default values
in use. Besides, it is a trap for pwm users that should take into
consideration this random default value.

Fix this by defaulting the property systematically to 0.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-06-16 10:41:01 +02:00
Guðni Már Gilbert be162087a9 dts: arm: st: l4: Move can1 node
The device tree includes CAN node can1 for all
STM32L4 chips when in fact they don't all support it.
This affects STM32L412xx and STM32L422xx.
Fixes #33896

Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
2021-04-01 07:27:56 -05:00
Shlomi Vaknin d9f40d53a6 dts: st: l4: add dac1 bindings
Add dac1 bindings to stm32l4 soc.

Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
2021-03-26 08:33:18 -04:00
Guðni Már Gilbert cd74a05011 dts: arm: st: l4: Add maximum-speed parameter to some STM32L4xx
Add optional maximum-speed parameter to USB nodes. This affects all
defined stm32l4xx, except stm32l4rx and stm32l4sx

Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
2021-03-17 11:29:53 +01:00
Gerard Marull-Paretas 4ba30e4336 dts: arm: st: add timer interrupts
Timer interrupts have been added for all STM32 SoC. H7 series already
had the interrupt definitions. The IRQ number and names have been taken
from the STM32Cube HAL header files.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-06-23 17:56:24 +02:00
Gerard Marull-Paretas 76f0d72e5d drivers: pwm: stm32: add support for polarity
Add support for the polarity flag in the STM32 PWM driver.

STM32 boards using PWM have been updated accordingly.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-06-19 15:18:50 +02:00
Erwan Gouriou d3664b063e drivers/spi: stm32: Modify use of "st,stm32-spi-fifo" compatible
On stm32 spi devices, there are 2 main IP variants, with and w/o
fifo. Fifo is not really used today, but still there is some
additional code handling fifo. Today this code is protected under
Kconfig symbol SPI_STM32_HAS_FIFO.
This code carries redundant information vs dedicated compatible
"st,stm32-spi-fifo", which is provided as unique driver compatible
for devices supporting this IP as opposed to use of "st,stm32-spi"
when fifo is not supported.

Having these 2 compatibles defined exclusively is not convenient for
migration to DT_INST as DT_INST macros contain compatible string and
hence it cannot be used to provide common compatible code for devices
defining different compatibles.

Based on these observations, review stm32 spi devices compatible
declarations. Devices supporting fifo will now declare both
compatibles, as proposed by dt spec: "[compatible] property value
consists of a concatenated list of null terminated strings,
from most specific to most general". Hence field will now be:
"st,stm32-spi-fifo", "st,stm32-spi"

This way, fifo enabled stm32 spi devices will generate both:
DT_INST_STM32_SPI_FOO and DT_INST_STM32_SPI_FIFO_FOO
As well as:
DT_COMPAT_ST_STM32_SPI and DT_COMPAT_ST_STM32_SPI_FIFO
So, DT_INST_STM32_SPI_FOO could be used for device initialization.
Also DT_COMPAT_ST_STM32_SPI_FIFO could be used for FIFO handling
code inside driver. Hence use it to replace Kconfig symbol
SPI_STM32_HAS_FIFO.


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-17 11:03:10 -06:00
Martin Jaeger 3d1834e5d6 dts: arm: stm32l452 dtsi files updated
Fixed warning for uppercase hex addresses and added stm32l452Xe.dtsi

Signed-off-by: Martin Jaeger <17674105+martinjaeger@users.noreply.github.com>
2019-12-13 17:02:40 -06:00
Francois Ramu 474c99c9ef drivers: usb/stm32: use dts information to populate clock settings
This patch populates "clocks" property in stm32 usb nodes
for clock related usb configuration code of each  dtsi files

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-07-16 09:08:51 -04:00
Yannis Damigos 30ac164771 dts: stm32l4: Fix USB phy node for stm32l432 and stm32l452
Fix USB phy node for stm32l432 and stm32l452, which contain
a USB controller and not a OTG FS controller.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2019-07-11 13:07:01 -05:00
Georgij Cernysiov 3b77737208 soc: st: add STM32L452XC
Adds STM32 L452 soc with L452xC variant. L452 has 160 KB SRAM;
therefore, mpu mem config has been extended; IRQ number is based on
'stm32l452xx.h'.

Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
2019-01-23 03:19:15 -06:00