Commit Graph

4 Commits

Author SHA1 Message Date
Erwan Gouriou 0aea704462 gpio: enable ports F G (and H) for stm32f1xx (stm32f4xx)
Some GPIO ports activation where missing since not used
on available soc/boards.
Since stm32 family increases, activation of these ports
should be made available.

Jira: ZEP-1551

Change-Id: I612d135b28ef255bc771599e33796671ff81d0ac
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-02-22 18:09:11 -06:00
David B. Kinder ac74d8b652 license: Replace Apache boilerplate with SPDX tag
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.

Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.

Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file.  Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.

Jira: ZEP-1457

Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 03:50:58 +00:00
Daniel Leung cf97ca685e doc: clock_control/stm32f1: Fix @file tag
The @file tag should follow by a file (or nothing for current file),
instead of file description. Fix it by separating the description.

Change-Id: Iabe3550568cdfdda6ad71be6fab3e8b5dfbeb940
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-04-15 22:06:42 +00:00
Maciek Borzecki 3f5af00529 clock_control/stm32f10x: introduce driver for STM32F10x RCC
The patch adds a driver for STM32F10x series RCC (Reset and Clock
Control) subsystem.

The module is primarily responsible for setting up of MCU's clock
tree. In particular the driver sets up SYSCLK, PLL (with source
configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this
functionality, the subsystem can enable/disable clock signal for
particular peripherals, thus reducing the power consumption of the MCU.

The driver implements clock control driver API. However, subsystem IDs
being HW specific are exposed in driver public header that must be
included by callers. The driver registers a single device using a common
name STM32_CLOCK_CONTROL_NAME. The device is initialized at
the PRIMARY level with priority 1. This allows the initialization to
take place right after SoC initialization routine.

The driver depends on selection of SOC_STM32F1X config option and is MCU
specific.

Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-16 18:11:18 +00:00