Commit Graph

82 Commits

Author SHA1 Message Date
Carles Cufi 51c1e45301 soc: nordic: Remove the nRF54L15 EngA
The production version of the nRF54L15 SoC is now available, so remove
the initial Engineering A (EngA) preview version.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2024-10-21 01:46:39 +01:00
Krzysztof Chruściński ffe6910e21 tests: kernel: interrupt: nested_irq: support nrf54h20_cpuppr
Add dedicated interrupt lines for nrf54h20_cpuppr. Similar exception
was already added to nrf54l15_flpr: 8742e2476.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2024-10-04 10:45:57 +01:00
Yong Cong Sin 8bfdff3cb1 irq: multilevel: add API to increment a multilevel IRQ
Unlike a normal IRQ, a multilevel IRQ can't be incremented by
simply `irq++`, as that would always increment the L1 of a IRQ,
regardless of its level. A function that understands the level
for which the IRQ operates in is required.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-10-02 10:08:19 +02:00
Yong Cong Sin 091d70de6b tests: kernel: interrupt: multilevel: test APIs with devicetree
Test multilevel-irq APIs with interrupt number generated from
the devicetree to make sure that they work in sync.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-10-02 10:08:19 +02:00
Karol Lasończyk 18086567dd tests: kernel: Add support for FLPR core in nRF54L15
Add support for production device.

Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
2024-08-29 12:02:35 +02:00
Marcin Szymczyk 68c48cd116 tests: kernel: interrupt: account for table offset
When verifying sw_isr_table, take into account custom offset,
like `CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET` in some
RISC-V SoCs.

Relates to #71948 and #73232.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-05-29 11:58:44 +02:00
Marcin Szymczyk 8742e24760 tests: kernel: interrupt: nested_irq: support nRF54L15 FLPR CLIC
Add support for VPR CLIC to `nested_irq` kernel test.
Verified on nRF54L15 FLPR for now.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-05-06 19:06:19 +02:00
Marcin Szymczyk fd79676c16 tests: kernel: interrupt: account for custom RISCV IRQ offset
`CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET` offsets IRQ in
vector table, align test to this functionality.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-05-06 19:06:19 +02:00
Radoslaw Koppel b0c83f328c arch: sw_isr_table: Update shared interrupts structures
This commit updates the definition of z_shared_isr_table_entry
to use _isr_table_entry instead of specially created z_shared_isr_client.

Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
2024-02-02 19:49:36 +01:00
Yong Cong Sin 2e37da45e5 tests: interrupt: sw_isr_table: fix index test for n+1 instance
The index test did not account for the level 2 table offset
when testing the (n + 1) instance, fix that.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-12-08 08:40:41 -05:00
Yong Cong Sin 7934a47332 tests: interrupt: sw_isr_table: use devicetree/Kconfig as ground truth
Updated the tests to use info from the devicetree or Kconfig as
ground truth and compare that with the output from the
functions under test.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-12-08 08:40:41 -05:00
Yong Cong Sin f3da086ac3 arch: common: sw_isr: make sure that the table index is within range
Assert that the `local_irq` of each levels should only ranges
from `0` to `CONFIG_MAX_IRQ_PER_AGGREGATOR`, so that it doesn't
overflow the other aggregators.

Also, assert that the output of `z_get_sw_isr_table_idx` shouldn't
overflow the ISR table.

Update the `sw_isr_table` tests to test the range of
`CONFIG_MAX_IRQ_PER_AGGREGATOR` instead of the entire range of
level bits.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-12-08 08:40:41 -05:00
Yong Cong Sin a28da922db tests: interrupt: refactor the sw_isr_irq_parent_table tests
Split the `sw_isr_irq_parent_table` test into one that tests
the IRQ table index function which is generic and should
always be tested, and one that tests multi-instance -related
functions which only work in interrupt controller drivers that
has multi-instance implementation.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-12-08 08:40:41 -05:00
Greter Raffael 8ed4876bed tests: kernel: also move the test_isr_dynamic to new ztest API
`test_isr_dynamic` for `CONFIG_GEN_SW_ISR_TABLE=n` was somehow
overlooked in commit b7f1e98724.

I'm disabling the irq at the end of the test. The babblesim for the
`nrf5340bsim_*` target walked into a timeout otherwise.

Signed-off-by: Greter Raffael <rgreter@baumer.com>
2023-11-15 10:01:22 +01:00
Yong Cong Sin ec93404a26 arch: common: irq: relocate internal functions into a private header
Relocate new and existing internal software-managed table
access functions from the public `sw_isr_table.h` into a
private header that should only be accessed internally.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-11-09 11:20:42 +01:00
Yong Cong Sin ad788a335f tests: interrupt: add testcase for functions in the sw_isr_table
Validate the following functions in the sw_isr_table:
- z_get_sw_isr_table_idx
- z_get_sw_isr_device_from_irq
- z_get_sw_isr_irq_from_device

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-11-09 11:20:42 +01:00
Benedikt Schmidt aa25e212d1 tests: fix thread function signatures
Fix thread function signatures to avoid stack corruption on thread exit.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2023-10-30 12:24:34 +01:00
Alberto Escolar Piedras 5dfc93b73c tests interrupt_offload: Set a proper interrupt for POSIX arch targets
The test assumed that interrupt line 5 was up for grabs, but it
is not in general. (For ex., on an nrf53_bsim this is the clock
interrupt, which cannot be hijacked).

Instead, for boards that define it, let's use the int line
used for offloading SW interrupts (which is defined for all posix
arch boards in tree)
And if this is not defined, let's skip the test.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-09-18 10:42:25 +01:00
Laurentiu Mihalcea 127696383f tests: kernel: interrupt: Add testcase for shared interrupts
This commit introduces a new testcase for shared interrupts.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-09-14 08:35:12 +02:00
Kumar Gala 99fee43f07 tests: interrupt: Fix armclang compiler warning
When building this test with the armclang compiler we get the following
warning:

tests/kernel/interrupt/src/dynamic_isr.c
tests/kernel/interrupt/src/dynamic_isr.c:23:32: error: 'used' attribute
ignored on a non-definition declaration [-Werror,-Wignored-attributes]

extern struct _isr_table_entry __sw_isr_table _sw_isr_table[];
                               ^
There is no need to add the __sw_isr_table on the extern, so remove it
to address the warning.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2023-04-11 09:35:42 +02:00
Kumar Gala 1c8f1cd590 tests: kernel: interrupt: workaround qemu_x86 interrupt issue
qemu_x86 seems to take an extra instruction after the sti instruction
(irq_unlock) happens before it posts the interrupts.  This can issues
if the instruction after the sti ends up reading the state that is
suppose to be updated by the ISR handler.

We see this behavior when building with LLVM.  To workaround this issue
we add an arch_nop() to provide an extra instruction to allow the
interrupts to post.

Opened zephyrproject-rtos/sdk-ng#629 to track qemu issue.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2023-02-21 16:17:20 -05:00
Gerard Marull-Paretas 178bdc4afc include: add missing zephyr/irq.h include
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-17 22:57:39 +09:00
Fabio Baltieri def230187b test: fix more legacy #include paths
Add a bunch of missing "zephyr/" prefixes to #include statements in
various test and test framework files.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2022-08-02 16:41:41 +01:00
Enjia Mai b7f1e98724 tests: kernel: move the interrupt tests to new ztest API
Migrate the testsuite tests/kernel/interrupt to the new ztest API.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-07-12 13:21:47 -04:00
Enjia Mai b3d442ec87 tests: kernel: move the direct interrupt test to arch testing
Move the direct interrupt test to tests/arch/x86/direct_isr. Two
reasons:
1. The direct interrupt is only for x86. It's arch-specific.
2. And it need extra gcc option to pass the build, that will
include testsuite number. Although it seems like we add a
extra testsuite for it, actually we can reduce whole tests
configuration in tests/kernel/interrupt. And also make this
test more generic as it used to be.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-07-12 13:21:47 -04:00
Carlo Caione e3f3aba989 arch: Use a common place for z_irq_spurious
Every architecture must export the z_irq_spurious definition. Just unify
that in one single header file.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-07 15:24:39 -04:00
Chen Peng1 bae794e300 test: interrupt: change the test interrupt line to a bigger one.
change the test interrupt line number to a bigger one, because
the low number usually will be used by other devices.

Signed-off-by: Chen Peng1 <peng1.chen@intel.com>
2022-06-23 09:08:43 +02:00
Gerard Marull-Paretas ade7ccb918 tests: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all tests to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 20:02:14 +02:00
Nazar Kazakov f483b1bc4c everywhere: fix typos
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
2022-03-18 13:24:08 -04:00
Andy Ross 53c8d61529 tests/kernel/interrupt: Don't wait so long just for a tick
There's no reason to wait a whole second here just to know if a tick
should have fired (though, yes, on some older/legacy/non-tickless
configurations, 128 ticks is actually more than a second).

Some simulators are very slow; busy waiting is expensive.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-26 13:34:45 -05:00
Enjia Mai e61e63e33f tests: interrupt: refine the interrupt testcases
This PR include 2 changes to refine the testcases:
1. Now we using IPI to trigger interrupt in testing instead of INT
   instruction, this means we don't need to hardcode the vector
   number. That can avoid some problem.

Fixes: #40374

2. Refined the test cases. Tigger interrupt by INT instruction and
   IPI cannot be masked by irq_disabled(). Unless it's a external
   interrupt, such as a timer. Now remove those incorrect part of
   these testcases.

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2022-01-18 13:24:28 -05:00
Naiyuan Tian 66c931dbd4 tests: interrupt: fix typos in the commits
While reading the code, find typos in the code commits.
tests:kernel:interrupt:src:dynamic_isr, line 110 and 115.

Signed-off-by: Naiyuan Tian <naiyuan.tian@intel.com>
2021-08-26 06:54:55 -04:00
Enjia Mai c2ac8fe7d7 acrn_ehl_crb: fix the incorrect configuration of timer IRQ priority
The default CONFIG_APIC_TIMER_IRQ_PRIORITY is 4, but it should be 1 for
ACRN. That's why the testcase failed due to no timer interrupt was
triggered.

And we also temporary adjust the testing IRQ for dynamic isr due to it
conflict with the IRQ of the APIC TSC deadline TIMER.

Fixes #36203.

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-08-03 07:30:15 -04:00
Nicolas Pitre b8d24ffb45 arm64: mitigate FPU-in-exception usage side effects
Every va_start() currently triggers a FPU access trap if FPU is not
already used. This is due to the fact that va_start() must copy FPU
registers that are used for float argument passing into the va_list
object. Flushing the FPU context to its owner and granting access to
the current thread is wasteful if this is only for va_start(),
especially since in most cases there are simply no FP arguments
being passed by the caller.

This is made even worse with exception code (syscalls, IRQ handlers,
etc.) where the exception code has to be resumed with interrupts
disabled upon FPU access as there is no provision for preserving an
interrupted exception mode's FPU context.

Fix those issues by simply simulating the sequence of STR instructions
that the va_start() generates without actually granting FPU access.
We limit ourselves only to exception context to keep changes to a
minimum for now.

This also allows for reverting the ARM64 exception in the nested IRQ
test as it now works properly even if FPU_SHARING is enabled.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2021-05-21 04:52:44 -05:00
Enjia Mai 04c736d98d tests: interrupt: refine the offload case not rely on delay timing
The interrupt offload testcases fail on some boards because the timing
of the delay is too short. Refine the testcases and make it not rely
on the delay timing.

Fixes #35097
Fixes #35241

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-05-20 17:34:09 -04:00
Enjia Mai e2f6b9536c tests: interrupt: fix coverity issue of newly added testcases
Should not use -1 as an input parameter for unsigned int. Use zero
instead of -1 as invaild interrupt number to fix coverity warning.

Fixes #35146
CID: 235994

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-05-13 22:02:47 -04:00
Enjia Mai c9c8cec3b6 tests: interrupt: add test cases of direct interrupt for arch x86 and posix
Add test cases of direct interrupt for arch x86 and posix.

We register two direct interrupt at build time, then triggering
interrupt and check if ISR handler has executed or not. We also
check irq_enable and irq_disable works.

Why we add an extra compiler option "-mgeneral-regs-only" to make
it works in arch x86. because there might be some existing x87
instructions executing inside interrupt context.

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-05-07 23:24:17 -04:00
Enjia Mai f70225863b tests: interrupt: add test cases of regular interrupt for arch x86
Add test cases of regular interrupt for arch x86. This tests basic
functionailty of IRQ_CONNECT(), irq_enable(), irq_disable(),
irq_lock(), irq_unlock().

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-05-07 22:19:08 -04:00
Enjia Mai 70f8f3302b tests: interrupt: add test cases of offloading job from isr
Add 3 test cases to test offload job from isr, include:

1. test_isr_offload_job_multiple()
Validate the offloaded work executes immediately or not depends on its
priority, and it offloads to different k_work.

2. test_isr_offload_job_identi()
Validate the offloaded work executes immediately or not depends on its
priority, and it offloads to the identical k_work.

3. test_isr_offload_job()
Use dynamic interrupt instead of irq_offload() to verify the offloaded
work.

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-05-07 18:24:32 -04:00
Nicolas Pitre f1f63dda17 arm64: FPU context switching support
This adds FPU sharing support with a lazy context switching algorithm.

Every thread is allowed to use FPU/SIMD registers. In fact, the compiler
may insert FPU reg accesses in anycontext to optimize even non-FP code
unless the -mgeneral-regs-only compiler flag is used, but Zephyr
currently doesn't support such a build.

It is therefore possible to do FP access in IRS as well with this patch
although IRQs are then disabled to prevent nested IRQs in such cases.

Because the thread object grows in size, some tests have to be adjusted.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2021-05-03 11:56:50 +02:00
Jennifer Williams a7ea624d7e tests: kernel: key has wrong type in test_prevent_interruption
The test_prevent_interruption() uses a key for the irq_lock(),
but the key has incorrect data type. This commit makes the key
unsigned int according to API docs.

Fixes #34023

Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
2021-04-06 14:37:24 -04:00
Enjia Mai 95cddd4df7 testsuite: utils: move the interrupt_util.h into testsuite
The interrupt_util.h provides utils of trigger irq, now move them into
testsuite. All of the needed test cases can make use of them.

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-03-30 08:18:23 -04:00
Eugeniy Paltsev 106528e48e tests: interrupts: generalize ARC-specific part for all ARC CPUs
Generalize ARC-specific interrupt triggering for all ARC CPUs
instead of ARCv2 only.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2021-03-25 07:23:02 -04:00
Enjia Mai b488b396bb tests: improve test cases for interrupt testing
Improve dynamic interrupt test cases of interrupt for platform such as
x86, x86_64, native_posix, this improve code coverage of it.

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-03-04 14:54:17 -05:00
Tomasz Bursztyka 50edd19f3a tests: Apply dynamic IRQ API change
Switching to constant parameter.

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00
Henrik Brix Andersen a115e44246 tests: kernel: interrupt: check that irq is not constantly pending
Extend check to determine a usable ARM NVIC IRQ line to verify that the
IRQ line is not always pending.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-08-14 13:35:39 -05:00
Henrik Brix Andersen f04f2e4278 tests: kernel: interrupt: add support for the ARM Cortex-M1
Add support for the ARM Cortex-M1 CPU to the kernel interrupt test case.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-08-14 13:35:39 -05:00
Sandeep Tripathy f54c57effe tests: kernel: interrupt: fix gic sgi priority
GICC_BPR has minimum legal values in secure and non-secure states.
'3' is the minimum BPR value leading to group and sub-group priority
as 'gggg.ssss'. In order to make an IRQ preemptible they need to
be in different priority group.

Hence to be generic priority values should be above '0x0f'.

IRQ0 - default priority  (low prio)
IRQ1 - 0x0   (highest prio)

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
2020-07-01 08:02:57 -04:00
Sandeep Tripathy ca6f04f554 tests: kernel: interrupt: Add gicv3 support
Generate SGI to self using own MPIDR.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
2020-07-01 08:02:57 -04:00
Kumar Gala a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00