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8 Commits

Author SHA1 Message Date
Andrew Boie 956089bcae xtensa: add config for toolchain version 
Use TOOLCHAIN_VARIANT to indicate what XCC toolchain release
to use.

Set a reasonable default for the RG-2016.4 toolchain release.
D_108mini, D_212GP, D_233L are only in RF-2016.4, set that
appropriately.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
 2017-05-18 07:18:36 -04:00
Andrew Boie b7aa6b7bd0 xtensa: optionally build reset vector code 
In real-world use-cases this isn't always needed.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
 2017-05-12 12:56:12 -04:00
Anas Nashif 09b239102a xtensa: xt-sim: mark it as a board with simulator features 
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
 2017-05-11 16:51:56 -04:00
David B. Kinder 36bb36475f spell: fix Kconfig help typos: /arch 
Fix misspellings in Kconfig help text

Change-Id: I2a753b57107f09073eb84ac757ac1e180ae89349
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
 2017-04-21 12:30:42 +00:00
Andrew Boie 11ee791b32 xtensa: build similar to other Zephyr arches 
* CONFIG_SOC is now properly set and we do not need a separate
  XTENSA_CORE build variable

* Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed

* There is no default SOC selection, it is now done explicitly in
  the board's defconfig

* CONFIG_<board name> now renamed to CONFIG_SOC_<board name in
  uppercase> to conform to established style.

Issue: ZEP-1711
Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
 2017-04-13 12:42:06 +00:00
Mazen NEIFER 3b95e3d729 Xtensa port: Added support for sample_controller core and set is as default. 
This core is not depreciated and compilationfor it is even faster than D_233L.

Change-Id: I6b8149ca9e879770c3ed0973ffb9304e2e3c8d8d
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
 2017-02-13 11:39:02 -08:00
Andrew Boie aa3ab35c88 xtensa: fixup license identifiers 
Master branch changed requirements for license headers while this
branch has been in development.

Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
 2017-02-13 08:04:27 -08:00
Mazen NEIFER 1cded67f38 Xtensa port: Started port to for Xtensa cores family. 
Added arch sub folder, make files and Kconfig files for a set of standard SoCs.

Change-Id: I4ee9cba966860072e55c95795d87356b665e4d49
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
 2017-02-13 08:04:26 -08:00