Commit Graph

20 Commits

Author SHA1 Message Date
Gerard Marull-Paretas fe2bca3020 drivers: fpga: move to POST_KERNEL
Devices should be initialized either in pre-Kernel or post-Kernel
stages.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-15 16:04:19 +02:00
Fabio Baltieri f45e7eddaa drivers: fpga: add an init priority config option
Add a Kconfig option for FPGA device initialization priority.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-08-24 15:35:37 +02:00
Christopher Friedt 64e6c90fc0 drivers: fpga: ice40: remove unnecessary include
The `<zephyr/posix/time.h>` header was unused in `fpga_ice40.c`
so remove it.

This fixes an error about `pthread_attr_t` not being defined.

Signed-off-by: Christopher Friedt <cfriedt@meta.com>
2023-08-23 10:06:00 +02:00
Anas Nashif bc03455f37 drivers: fpga: imply CRC
This driver needs CRC, so select it instead of relying on it set by
default.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-08-18 08:52:16 +03:00
Gerard Marull-Paretas 3f2c2d4130 drivers: spi: make SPI dt-spec macros compatible with C++
As of today it is not possible to use SPI dt-spec macros in C++,
something known and documented. The main reason is because `cs` property
is initialized using a compound literal, something not supported in C++.
This PR takes another approach, that is to not make `cs` a pointer but a
struct member. This way, we can perform a regular initialization, at the
cost of using extra memory for unused delay/pin/flags if `cs` is not
used.

Fixes #56572

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-24 21:29:55 +02:00
Gerard Marull-Paretas 0ebe14beb4 sys: util: migrate all files to DIV_ROUND_UP
ceiling_fraction is deprecated, use DIV_ROUND_UP.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-11 12:00:37 +02:00
Henrik Brix Andersen c41dd36de2 drivers: kconfig: unify menuconfig title strings
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".

Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2023-03-28 15:06:06 +02:00
Armin Brauns a6e5135381 drivers: fpga: ice40: fix busy delay loop
This was being optimized out entirely by certain compiler configurations.

Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
2023-03-14 11:17:35 +01:00
Armin Brauns d0762e5439 drivers/fpga: ice40: use microsecond resolution for reset time
The 200ns reset time specified in the datasheet are a minimum time; and the
nanoseconds were being rounded to whole microseconds anyway.

Also make it the same type as `config_delay_us` (`uint16_t`).

Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
2023-03-14 11:17:35 +01:00
Armin Brauns 2f6dff59c5 drivers/fpga: ice40: use k_usleep instead of busy loop in SPI mode
The 200ns reset time are a minimum value, there is no need to enforce
precise timing (and thus manual per-device calibration) here.

Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
2023-03-14 11:17:35 +01:00
Armin Brauns 8aec9dd552 drivers/fpga: ice40: fix minimum config delay
From FPGA-TN-02001-3.3 "iCE40 Programming and Configuration":

> After driving CRESET_B High or allowing it to float High, the AP must
> wait a minimum of 1200 µs, allowing the iCE40 FPGA to clear its internal
> configuration memory.

Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
2023-03-14 11:17:35 +01:00
Chris Friedt 22fe674a9c drivers: fpga: ice40: add support for the Lattice iCE40 series
Add support for the Lattice iCE40 series FPGAs.

Fixes zephyrproject-rtos#48317

Signed-off-by: Chris Friedt <cfriedt@meta.com>
2022-11-17 09:17:44 -05:00
Michal Sieron 702caf1c7e samples: boards: Add Qomu board sample
First pads are being configured for use by the FPGA.
Then CPU loads usbserial bitstream.
Finally it reenables clocks, sets up USB PID and waits for device to
enumerate.

Also disable software resets in used clocks.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
2022-10-20 15:41:09 +02:00
Gerard Marull-Paretas fb60aab245 drivers: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:58:21 +02:00
Mateusz Sierszulski 06e4f36b4b fpga controller: drivers: add ZynqMP driver
This commit adds support for fpga driver on ZynqMP SoC.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2022-04-21 13:00:57 +02:00
Mateusz Sierszulski 6d56b82942 drivers: fpga: connect dts node with fpga driver
This commit connects the eos_s3 fpga driver with fpga dts node.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2022-04-08 15:54:33 -07:00
Gerard Marull-Paretas 95fb0ded6b kconfig: remove Enable from boolean prompts
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:

sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-09 15:35:54 +01:00
Mateusz Sierszulski c09dfb3bf6 drivers: fpga controller: add shell support
This adds shell support for FPGA drivers.

Signed-off-by: Mateusz Sierszulski <msierszulski@internships.antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
2021-09-03 09:54:00 -04:00
Mateusz Sierszulski a64ce1fc6b drivers: fpga controller: add eos_s3 fpga driver
This adds driver for EOS_S3 SoC FPGA.

Signed-off-by: Mateusz Sierszulski <msierszulski@internships.antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
2021-09-03 09:54:00 -04:00
Mateusz Sierszulski 2c718b2726 drivers: fpga controller: add fpga api
This adds new FPGA controller which allow to control FPGA chips.

FPGA controller has been created to enable bitstream loading
into the reprogrammable logic. It adds completely new API,
which enables to check status of the FPGA chip, power it on
or off and reset it.

Signed-off-by: Mateusz Sierszulski <msierszulski@internships.antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
2021-09-03 09:54:00 -04:00