Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This fix allows Renode to resemble the time flow of the hardware more
precisely. The performance value was established manually, there is no
indication in the docs on what is the average performance.
It allows tests/posix/common/portability.posix to pass, but fails on
tests/kernel/lifo/lifo_usage/kernel.lifo.usage.
The latter also fails on hardware.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Remove most unnecessary instances of `export` and `cmake` use that can
instead be replaced with `zephyr-app-commands` or similar. This is to
avoid documentation using different mechanisms to describe the same
actions and in preparation for documenting `west build` everywhere.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Be consistent in how board docs are named and move all to index.rst.
This will make the URL to the board documentation predictable and easier
to remember.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The test suite will use the m2gl025_miv.resc Renode script to load the
platform.
Signed-off-by: Dawid Wojciechowski <dwojciechowski@internships.antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Removed Console dependencies from shell uart backend.
Generated define: CONFIG_UART_SHELL_ON_DEV_NAME for each board.
Fixes#10191
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
Update the uart_miv driver to get params like name, addr, baud-rate,
clock freq from DTS generated defines. Fixup related board and soc code
as needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add minimal DTS support for the m2gl025_miv. The dts just has the core,
SoC, PLIC, and UART described. We still get memory related info from
Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds support for Microsemi Mi-V RISC-V softcore CPU
running on the M2GL025 IGLOO2 FPGA development board.
signed-off-by: Karol Gugala <kgugala@antmicro.com>
Mateusz Holenko