Commit Graph

35 Commits

Author SHA1 Message Date
Andrew Boie da4024b1f7 Kconfig: CONFIG_USERSPACE is experimental
Indicate to users that this feature isn't fully baked yet.
This will be reverted for 1.11 release.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-13 13:40:21 -07:00
Andrew Boie 2b6abf6f89 kernel: USERSPACE implies HW_STACK_PROTECTION
Userspace is built on top of hardware stack protection and assumes
it is there. We can't enable this unless ARCH_HAS_USERSPACE is defined
anyway.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-11 20:27:10 -04:00
Andrew Boie 9f70c7b281 kernel: reorganize CONFIG_USERSPACE
This now depends on a capability Kconfig.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-12 12:46:36 -07:00
Anas Nashif d414e7c7ee kconfig: move fatal error handler to arch options
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif 8379b7b433 kconfig: move interrupt options into arch menu
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif 46f66f4295 kconfig: generalised stack protection options
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
David B. Kinder 3561c73ece spell: Kconfig help typos: /arch
Fix misspellings in Kconfig help text and made spelling of
RX and TX consistent (from reviewer comments)

Change-Id: Ie9d4c3863cd210e7a17b50a85a7e64156b6bf3d7
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-04-24 20:14:53 +00:00
Andrew Boie b2e136c5f0 gen_isr_tables: make vector offset a hidden option
If this is set incorrectly things will break all over the place.
Needs a default defined per-arch and left alone.

Change-Id: I3f8c842937a240297ee21589a22a7a9e51dbdfad
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:49:17 +00:00
Mazen NEIFER 1cded67f38 Xtensa port: Started port to for Xtensa cores family.
Added arch sub folder, make files and Kconfig files for a set of standard SoCs.

Change-Id: I4ee9cba966860072e55c95795d87356b665e4d49
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:26 -08:00
Andrew Boie 1927b3d020 gen_isr_tables: New static interrupt build mechanism
This is a new mechanism for generating interrupt tables which will
be useful on many architectures. It replaces the old linker-based
mechanism for creating these tables and has a couple advantages:

 1) It is now possible to use enums as the IRQ line argument to
    IRQ_CONNECT(), which should ease CMSIS integration.
 2) The vector table itself is now generated, which lets us place
    interrupts directly into the vector table without having to
    hard-code them. This is a feature we have long enjoyed on x86
    and will enable 'direct' interrupts.
 3) More code is common, requiring less arch-specific code to
    support.

This patch introduces the common code for this mechanism. Follow-up
patches will enable it on various arches.

Issue: ZEP-1038, ZEP-1165
Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 01:27:58 +00:00
Ramesh Thomas 444ecafeee kernel: Remove redundant TICKLESS_IDLE_SUPPORTED option
This flag is no longer necessary and TICKLESS_IDLE will be
enabled by default if SYS_POWER_MANAGEMENT is enabled.

Jira: ZEP-1325
Change-Id: Ic6cd4b8dc0a17c6a413cabf6509b215a4558318d
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-02-08 13:02:34 +00:00
David B. Kinder ac74d8b652 license: Replace Apache boilerplate with SPDX tag
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.

Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.

Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file.  Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.

Jira: ZEP-1457

Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 03:50:58 +00:00
Jean-Paul Etienne cd83e85edc arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.

1) exceptions/interrupts/faults are handled at the architecture
   level via the __irq_wrapper handler. Context saving/restoring
   of registers can be handled at both architecture and SOC levels.
   If SOC-specific registers need to be saved, SOC level needs to
   provide __soc_save_context and __soc_restore_context functions
   that shall be accounted by the architecture level, when
   corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.

2) As RISC-V architecture does not provide a clear ISA specification
   about interrupt handling, each RISC-V SOC handles it in its own
   way. Hence, at the architecture level, the __irq_wrapper handler
   expects the following functions to be provided by the SOC level:
   __soc_is_irq: to check if the exception is the result of an
                 interrupt or not.
   __soc_handle_irq: handle pending IRQ at SOC level (ex: clear
                     pending IRQ in SOC-specific IRQ register)

3) Thread/task scheduling, as well as IRQ offloading are handled via
   the RISC-V system call ("ecall"), which is also handled via the
   __irq_wrapper handler. The _Swap asm function just calls "ecall"
   to generate an exception.

4) As there is no conventional way of handling CPU power save in
   RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
   functions just unlock interrupts and return to the caller, without
   issuing any CPU power saving instruction. Nonetheless, to allow
   SOC-level to implement proper CPU power save, nano_cpu_idle and
   nano_cpu_atomic_idle functions are defined as __weak
   at the architecture level.

Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-13 19:52:23 +00:00
Anas Nashif cfbe9b05a1 kernel: rename NANOKERNEL_TICKLESS_IDLE_SUPPORTED
rename NANOKERNEL_TICKLESS_IDLE_SUPPORTED to
TICKLESS_IDLE_SUPPORTED and remove nanokernel occurances in Kconfig
files.

Make TICKLESS_IDLE depend on hardware that supports it.

Change-Id: I6a2e4fb0f7cf4b45475b48e71823ea089ee98759
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:35 +00:00
Benjamin Walsh b12a8e0914 kernel: introduce single-threaded kernel
For very constrained systems, like bootloaders.

Only the main thread is available, so a main() function must be
provided. Kernel objects where pending is in play will not behave as
expected, since the main thread cannot pend, it being the only thread in
the system. Usage of objects should be limited to using K_NO_WAIT as the
timeout parameter, effectively polling on the object.

Change-Id: Iae0261daa98bff388dc482797cde69f94e2e95cc
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 16:17:39 -05:00
Benjamin Walsh 48db0b3443 arch/all: simpler _SysFatalErrorHandler()
- does not pull in printk(), for potential footprint gain
- does not pull in k_thread_abort(), for single-threaded systems

Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Change-Id: Ibc6a198b81a6cd73117d1e85aa05b92a4501a34d
2016-12-15 16:17:39 -05:00
Ramesh Thomas a3dc53f2a6 power_mgmt: Do not notify deep sleep if bootloader does context restore
Some bootloaders have power management support to restoer context
upon resume from deep sleep. In such cases, the OS startup code
should call the notification hook. Create Kconfig flags to configure
this option.

Jira: 1257
Change-Id: I9f40c5fa077c2f17dc8e9f11604c3ed17e549ed5
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-11 20:40:53 +00:00
Ricardo Salveti b0e0c51b47 arm: move atomic operations selection to the Cortex-M Kconfig
Builtin might not be available for ARMv6 (Cortex-M0/M0+) depending on
the toolchain used (not available by Zephyr's SDK GCC), so move the
atomic operations selection to the Cortex-M family Kconfig file.

Change-Id: I20a5a0c5fdd2bcff2d304139f5a7e8502fdb1cb3
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
2016-10-11 20:47:49 +00:00
Andrew Boie 6a1474e75b nanokernel: support GCC compiler atomic builtins
Arches now select whether they want to use the GCC built-ins,
their own assembly implementation, or the generic C code.

At the moment, the SDK compilers only support builtins for ARM
and X86. ZEP-557 opened to investigate further.

Change-Id: I53e411b4967d87f737338379bd482bd653f19422
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-18 23:20:52 +00:00
Kumar Gala 9ec2f3be80 Cleanup whitespace in Kconfig files
Convert leading whitespace into tabs in Kconfig files.  Also replaced
double spaces between config and <prompt>.

Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-25 13:28:07 -05:00
Andrew Boie ff872dc349 build: rename non-generated linker scripts to .ld extension
Avoids confusion with .gitignore rules, which were inadequate to
cover all the places where these files are found. At least in
VIM, these files are now syntax highlighted correctly.

Change-Id: I23810b0ed34129320cc2760e19ed1a610afe039e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-09 18:09:26 +00:00
Andrew Boie 9433895954 nios2: basic build, non-functional
Basic build framework for Nios2. Everything is stubbed out,
we just want to have a build going so that we can start to
parallelize implementation tasks.

This patch is not intended to be functional, but should be
able to produce a binary for all the nanokernel-based
sanity checks.

Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-03 23:18:45 +00:00
Anas Nashif a02c34ef0b soc: introduce SoC families and series
Add additional layers when defining SoCs to allow reuse among SoCs
of the same family and architecture.

The Board is the first location where we search for a linker.cmd file,
if not found we look for the linker file in
arch/<arch>/soc/<family>/<series>

Change-Id: I51d5e9a056220d0bd2ae0fa31474ffe63568e698
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-18 21:24:59 +00:00
Ramesh Thomas bb19e6f82f power_mgmt: Make names consistent with new RFC
Changed names of Kconfig flags, variables, functions, files and
return codes consistent with names used in the RFC. Updated
relevant comments to match the changes.

Origin: Original
Change-Id: Ie7941032d7ad7af61fc02928f74538745e7966e8
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-03-26 14:35:11 -04:00
Ramesh Thomas 3888735e0d adv_power:Advanced Power Management APIs
This is part of an ongoing development of power management
support in zephyr. This implementation builds upon an existing
hook interface and adds more enhancements. This was tested
with reference implementations on quark_d2000 and quark_se.

Change-Id: I28092b7ec90ce1f1cc661cf99ca88708910c8eb2
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-02-12 11:20:32 -08:00
Sergio Rodriguez 4dee326306 tickless idle x86: Tickless idle support on nanokernel for x86
Modifications to timer drivers and interrupt setup, to manage
the tickless idle for the x86 architecture

Change-Id: Ie02d484b7e5636de6ea382ba2eeed57e704c8498
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
2016-02-11 19:10:24 +00:00
Anas Nashif 10bb38c186 Use SoC instead of platform.
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.

Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif fdb1daf786 kconfig: add board configurations
First step for adding the new board layer. Create configurations for the
various boards we support on x86 under boards with the new Kconfig variables
defining them.

The board selection is optional, that means you will be able to run

 make menuconfig

and create your own .config and select any SoC.

Change-Id: If08e88e9675d13f0f0501ef6750b9424b15f5dc8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:10 -05:00
Anas Nashif 2d762243fd kconfig: add BOARD Kconfig variable for defining boards
This variable (CONFIG_BOARD) will store the textual form of the
platform name and will be used for locating files related to the
board in the source tree.

Change-Id: I3c8a05ed428451a6785799a5492f0dd14682f208
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:10 -05:00
Anas Nashif 66233116ff kconfig: define CONFIG_PLATFORM only once
define CONFIG_PLATFORM only once in arch/Kconfig and set it
for every platform.

Change-Id: I8554bb36d2d15c3ee71fa63dfc3a763ebca956ee
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:04 -05:00
Anas Nashif 77ba3c3b8b kconfig: define architecture as a kconfig variable
Do not depend on environment variables and use a kconfig variable
for defining the architecture.

In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.

Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Javier B Perez Hernandez f7fffae8aa Change BSD-3 licenses to Apache 2
Change all the Intel and Wind River code license from BSD-3 to Apache 2.

Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:29 -05:00
Anas Nashif 745c2b66fd Remove sourcing of arch kconfig to root
Change-Id: I052721288a58ae27c49b59f8e42bdab469f3b2f3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Juan Manuel Cruz d15251fec5 Kbuild: Kconfig license headers.
This commit add license headers to Kconfig files.

Change-Id: I79e60263b8c7b696463ecc84b8ad411af5415117
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:10 -05:00
Juan Manuel Cruz 132649f2cc Kconfig symbols for arch directory.
This commit adds the Kconfig files that describe the CONFIG
    symbols that belongs to the arch directory and subdirectories.

Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Change-Id: I744225ddaa5e2b45113ca049457a8f9925ebe4c2
2016-02-05 20:14:04 -05:00