The number of IRQ priority bits was incorrectly set to 3 instead
of 2, which is the correct number for Cortex-M0+.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
After porting from h5 to f7 i noticed that not all mcus have
cpu node labels. Added cpu0 node labels to all stm32 dts.
Signed-off-by: Kacper Dalach <dalachowsky@gmail.com>
Revert "dts: bindings: LPtimer of stm32 has a x2 factor on its clock"
The stm32u5 lptim clock source has no prescaler to divide the
the LPTIM input clock frequency : no property required.
This reverts commit 572b286010.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
r8a779f0 is also know as S4, this SoC is part of the Gen4 SoC series,
has 8 Cortex-A55 and a dual core lockstep Cortex-R52 processor.
SCIF0 is dedicated to Zephyr and SCIF3 to Linux.
**Control Domains**
IMPORTANT: This SoC is divided into two "domains":
- Application domain contains some peripherals as well as A55 & R52 cores.
- Control domain that contain a G4MH/RH850 MCU and other peripherals.
In order to access control domain peripherals such as gpio4-7 and CAN-FD
from application domain, the G4MH MCU has to unlock a protection
mechanism from control domain buses.
"Protected" controllers will be flagged in gen4 device trees,
warning users that they need to flash a custom G4MH firmware
to unlock access to these controllers.
**Clock controller**
This SoC clock controller is offering "domains"
for each world (Zephyr/Linux).
These domains are several "entry points" to the clock controller
which are arbitrated to avoid a world from turning off a clock needed
by another one.
We decided to use the same domain as Linux because the
security mechanism as to be implemented before accessing
another domain.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Add support of r8a779f0 cpg driver.
r8a779f0 soc has its own clock tree.
Gen4 SoCs common registers addresses have been added in header.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
The shi module in npcx4 supports the enhanced buffer mode.
Add a new compatible string "nuvoton,npcx-shi-enhanced" for it.
Then the shi driver can determine if it should use the enhanced buffer
mode based on the compatiable string.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
By making short inputs optional, the user can bypass short-events all
together if necessary (e.g. custom button-press listener).
Signed-off-by: Juliane Schulze <juliane.schulze@deveritec.com>
This add regulator driver for Smartbond DA1469X SOC.
Driver can control VDD, V14, V18, V18P, V30 rails,
full voltage range supported by SOC is covered.
For VDD, V14, V18, V18P DCDC can be configured.
Special VDD_CLAMP (always on) and VDD_SLEPP are added
to allow configuration of VDD in sleep modes.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Add an option to drive inactive columns to inactive state rather than
high impedance. This is useful if the matrix has isolation diodes for
every key, as it allows the matrix to stabilize faster and the API for
changing the pin value is more efficient than the one to change the pin
configuration.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Only RTC can be used as the idle timer for cortex-m systick. Set the
chosen node as RTC by default.
The idle timer will be enabled only if PM management is set.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Rather than configuring in serial_wakeup sample, define LPUART1 wakeup
line in wl.dtsi file.
Additionally make few cosmetic changes to nucleo_wl55rj overlay in
serial wakeup sample.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add soc power management for the STM32F4x chips.
One low power state is added supported by all chips from the family -
the Stop mode with voltage regulator in low-power mode.
The Stop mode for STM32F chips has to work with the IDLE timer -
CORTEX_M_SYSTICK_IDLE_TIMER, because PLL and HSI are disabled in the
Stop mode (Systick is not clocked). The only possible wakeup source is
RTC, which works as a IDLE timer for the Systick.
The exit latency may need to be adjusted per system, depending on the
system tick frequency and other variables.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
On STM32WL, the backup memory is defined as part of the TAMP peripheral.
This seems to be a deviation from the stm32 family where this memory is
defined as part of the RTC.
The STM32WL reference manual shows that tamp_pclk is connected to
rtc_pclk. This means that the clock required to run the TAMP peripheral
is the same as the RTC's. A quick port of BBRAM on STM32WL is achieved
by instanciating the bbram device as a child of the RTC and by modifying
the address offset to the first backup register from the rtc base
address.
Signed-off-by: Adrien Bruant <adrien.bruant@aalberts-hfc.com>
This commit moves configuration of hfxo from headers defined on board level
to device trees of SoCs.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
Add dummy interrupt id until we can support UART interuppt
on i.MX8MP in order to fix compilation warnings.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
This commit introduces the SOF host DMA driver.
This driver is used by NXP platforms in the context of
SOF's host component to copy data from the host memory
to the firmware (local) memory. This is possible because
NXP platforms can access the host memory directly w/o
an actual DMA engine.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Adds a clock control device for a PWM node, allowing the PWM
to be controlled using the clock control API.
It is a similar idea to the device driver in linux:
linux/Documentation/devicetree/bindings/clock/pwm-clock.yaml
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Split the common keyboard scanning code out of the ITE specific driver
and use the generic code instead.
Note that this changes few timing defaults, the change is not
significant though so I suspect there's no difference in practice.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
- added example of usage Infineon CAT1 i2c driver
- added note that pinctrl nodes need to be configured
as open-drain and input-enable.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Setting slew-rate property is not supported on Kinetis KE series
and the value will not have effect, so this property should not
be required.
We are also planning to reuse the Kinetis pin control binding and
associated driver for NXP S32K1xx devices, which doesn't support
setting the slew-rate rate as well.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add Verdin iMX8M Plus board with i.MX8MP SoC and ARM Cortex-M7 processor.
Add two targets (DDR and ITCM) for the iMX8M Plus board.
Port and documentation are based on NXP MIMX8MM EVK board.
This code is intented to be used with the Cortex-M7.
Signed-off-by: Gabriel Freitas <gabriel.freitas@toradex.com>
Add support for UART1 usage by adding uart1 node and configuration
to the i.MX 8ML devicetree include.
Signed-off-by: Gabriel Freitas <gabriel.freitas@toradex.com>
Add Renesas rzt2m gpio driver with basic functionality.
It supports pin mode configuration and writing/reading to/from gpio ports.
Includes dts changes to build blinky sample.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
This adds a new driver for Renesas RZ/T2M.
The driver allows configuration of pin direction,
pull up/down resistors, drive strength and slew rate,
and selection of function for a pin.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This adds a UART driver for the Renesas RZ/T2M
Serial Communication Interface.
The driver implements:
* Polling API,
* Interrupt-driven API.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This adds a new SoC: SOC_RENESAS_RZT2M
and a new board: rzt2m_startek_kit
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Co-authored-by: Roman Dobrodii <rdobrodii@antmicro.com>
cyliang tw