This fixes a build issue on esp32 that was introduced recently with the
merge of an old PR.
Include the register headers in soc.h rather than soc.c and make them
available to other code via soc.h
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
On 'drivers/i2c_esp32.c' there are functions useful for other
drivers. Functions and struct went moved to:
* arch/xtensa/soc/esp32/peripheral.h
* arch/xtensa/soc/esp32/soc.h
* include/drivers/gpio/gpio_esp32.h
Signed-off-by: Vitor Massaru Iha <vitor@massaru.org>
The entry point can and therefore should be set by linker
scripts. Whenever possible one should express things in the source
language, be it .c or .ld, and not in code generators or in the build
system.
This patch removes the flag -eCONFIG_KERNEL_ENTRY from the linker's
command line and replaces it with the linker script command
ENTRY(CONFIG_KERNEL_ENTRY)
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Both variables were used (with the same value) interchangeably
throughout CMake files and per the discussion in GH issue,
ZEPHYR_BASE is preferred.
Also add a comment with explanation of one vs. the other.
Tested by building hello_world for several boards ensuring no errors.
Fixes#7173.
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
lib/libc/minimal/source/CMakeLists.txt and
lib/libc/minimal/source/stdout/CMakeLists.txt was introduced in
12f8f7616 but it is not used by the build system. CMakeLists.txt in
the parent dir lib/libc/minimal/CMakeLists.txt adds C files to the
target with the lines like:
${CMAKE_CURRENT_SOURCE_DIR}/source/stdlib/atoi.c
${CMAKE_CURRENT_SOURCE_DIR}/source/stdlib/strtol.c
To make other empty CMakeLists.txt explicit, this commit adds a
comment line to them.
Signed-off-by: Yasushi SHOJI <y-shoji@ispace-inc.com>
IRQ priorities for CAVS and DW were previously defined in Kconfig.
They are now defined via DTS and removed from Kconfig.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Add bit definitions and set M/N divider ownership in
i2s_initialize.
Changes to comply with coding guidelines
Changes to address review comments
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
Added a function to obtain the reference clock frequency value based on
SoC's bootstraps.
Added M/N divider base address in SoC header file
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
At least one of my WROOM boards has trouble getting the APPCPU
started, that was magically getting better when I started adding
printk's to debug. It turns out that UART output (and NOT simply idle
cycles of delay) was the magic dust to fix things. As this SMP
implementation is reverse engineered voodoo to begin with, this hack
should be acceptable in the medium term.
See in-file comments on smp_log() for details.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
In preparation for introducing a warning.
Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.
Suggested by Kumar Gala.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The Kconfig option TOOLCHAIN_VARIANT (not to be confused with
ZEPHYR_TOOLCHAIN_VARIANT) is a legacy configuration option that has
very few use-cases and can easily be dropped.
It's functionality is easily covered by CONFIG_X86_IAMCU and
ZEPHYR_TOOLCHAIN_VARIANT.
This commit removes all references of it from Zephyr.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
patch add clock frequency and interrupt property to uart
node in intel_s1000.dtsi. Include soc.h after types.h to
prevent build error.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Fix the ns16550 uart driver and relevant SoCs accordingly.
All generic settings are now DTS based.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Implements the driver for Intel CAVS I2S. Only Playback
is currently supported.
Change-Id: I7b816f9736dc35e79a81d3664d6405dc0aac15b4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable the CAVS DMA on intel_s1000. Also, introduce a test to
validate the DMA.
Change-Id: I2ff233c45cfd8aea55e254d905350a666aa649a0
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduce the Intel CAVS DMA. This is based out of the DesignWare
DMA IP but the register offset and bits have been changed in some
cases. However, the fundamental definition for the register field
has not been changed. Hence the registers begin with "DW_" to
indicate the Designware origin.
This driver currently supports the single block mode and linked list
multi-block mode. Scatter-Gather is not supported.
Change-Id: I33a8ed5141d9236167de50e14d3d407e95d6f553
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 has multiple levels of interrupts consisting of core, CAVS
Logic and designware interrupt controller. This patchset modifies
the regular gen_isr mechanism to support these multiple levels.
Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 makes use of DesignWare IP for I2C.
Change-Id: Ie091318c5959b95e1febeb5cefa440f35a6d144b
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable GPIO handling for intel_s1000. It uses a DesignWare IP.
Change-Id: I522534935e4ef3a56d93aca669f6de961d927481
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 uses DesignWare IP for UART. National Semiconductor
16550 (UART) component specification is followed in this IP.
Change-Id: Ied7df1dc178d55b6dbe71d729d6383ba07274ea4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000_crb board makes use of the intel_s1000 SoC. It has
a built-in ROM which gets executed upon applying power. It then
executes the secondary bootloader followed by the FW (like zephyr).
Change-Id: If334c359b4372a56997c3b2e1eb9250e80847f07
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 is an SoC having cavs21_LX6HiFi3_RF3_WB16 as the CPU which
belongs to Xtensa family. This is being used in intel_s1000_crb.
Change-Id: Ic424aa77557bf31024ddbf3f1d76b72a4adb8f66
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
ESP-IDF commit cb31222e added the dependency on a file named
"sdkconfig.h", which is equivalent to "autoconf.h" generated by kbuild
used in Zephyr. It does not depend on anything from that file, though,
so just provide an empty file to keep the compiler from complaining.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Include `soc.h` first, which will include the ESP-IDF headers -- which
will define the `BIT()` macro without checking if they're already
defined, like the Zephyr headers do.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
When in SMP mode, the nested/irq_stack/current fields are specific to
the current CPU and not to the kernel as a whole, so we need an array
of these. Place them in a _cpu_t struct and implement a
_arch_curr_cpu() function to retrieve the pointer.
When not in SMP mode, the first CPU's fields are defined as a unioned
with the first _cpu_t record. This permits compatibility with legacy
assembly on other platforms. Long term, all users, including
uniprocessor architectures, should be updated to use the new scheme.
Fundamentally this is just renaming: the structure layout and runtime
code do not change on any existing platforms and won't until someone
defines a second CPU.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Simply define the Kconfig variables in this patch so they can be used
in later patches. Define MP_NUM_CPUS correctly on esp32. No code
changes.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is a mostly-internal API to start a secondary system CPU, with an
implementation for the ESP-32 "APP" cpu. Exposed in kernel.h because
it's plausibly useful for asymmetric MP code managed by an app.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This python script reads the core-isa.h interrupt definitions (via
running a template file through the toolchain preprocessor to generate
an input file) and emits a fully populated, optimized C handling code
that binary searches only the declared interrupts at a given level and
correctly detects spurious interrupts (and/or incorrect core-isa.h
definitions).
The generated code, alas, turns out not to be any faster than simply
searching the interrupt mask with CLZ (er, NSAU in xtensese), though
it could be faster in theory if the compiler made different choices,
see comments. But I like this for the robustness of the fully
populated search trees and the checking of level vs. mask.
This simply commits the script output into the source tree, including
some checking code to force a build error if the toolchain changes the
headers incompatibly. It would be better long term to have these
headers be generated at build time, but that requires more cmake fu
than I have.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.
Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.
This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.
For users that just want to continue their work with minimal
disruption the following should suffice:
Install CMake 3.8.2+
Port any out-of-tree Makefiles to CMake.
Learn the absolute minimum about the new command line interface:
$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..
$ cd build
$ make
PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
Also provide their prototypes in `soc.h`. This should help
readability, since some ROM functions, with their names as provided by
Espressif, have sometimes the same prefix as Zephyr APIs.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Move all QEMU related defines to the boards and cleanup xtensa platforms
which were marked to be QEMU capable by mistake.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Esp-idf defines the BIT macro that is also defined in Zephyr's
misc/util.h. Fix the issue by including the esp-idf headers first, so
that a check in util.h won't redefine the macro if it's already
defined.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
- .text, .text.*, .literal, .literal.* had no matching input section
rule and were being passed to the output binary verbatim. These
are all now in the output "text" section as intended.
- various rules in the data section were unnecessarily using KEEP().
- SW_ISR_TABLE wasn't included in linker script anywhere and was
ending up in its own section, and not the data section as intended.
- noinit section didn't exist at all, now defined.
Issue: ZEP-2508
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This cleans up the exception handling by removing the table declaration
from xtensa_intr_asm.S, and removing the unused
_xt_set_exception_handler() function.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
The Xtensa port was the only one remaining to be converted to the new
way of connecting interrupts in Zephyr. Some things are still
unconverted, mainly the exception table, and this will be performed
another time.
Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since
IRQs can't change priority on Xtensa: while the architecture has the
concept of interrupt priority levels, each line has a fixed level and
can't be changed.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This provides basic GPIO support, with interrupts, and the ability to
read and write to ports on a pin-by-pin basis.
Jira: ZEP-2286
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
The first stage bootloader, part of the ESP32 ROM, already sets up
a stack that's sufficient to execute C programs. So, instead of
implementing __stack() in assembly, do it in C to simplify things
slightly.
This ESP32-specific initialization will perform the following:
- Disable the watchdog timer that's enabled by the bootloader
- Move exception handlers to IRAM
- Disable normal interrupts
- Disable the second CPU
- Zero out the BSS segment
Things that might be performed in the future include setting up the
CPU frequency, memory protection regions, and enabling the flash
cache.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Anas Nashif