zephyr

Commit Graph

Author	SHA1	Message	Date
Maureen Helm	cf1d374276	boards: rv32m1_vega: Introduce zero-riscy configuration Introduces a new rv32m1_vega board configuration for the zero-riscy core. It assumes that the soc has been reconfigured with openocd to boot to the zero-riscy core instead of the ri5cy core. Refactors the board-level device tree so the ri5cy and zero-riscy configurations share common definitions for the led, button, and sensor nodes. Tested with: - samples/hello_world - samples/synchronization - samples/basic/blinky - samples/basic/button - samples/sensor/fxos8700 Signed-off-by: Maureen Helm <maureen.helm@nxp.com>	2019-05-06 14:52:17 -05:00
Henrik Brix Andersen	766abcc0ad	boards: rv32m1_vega: enable the onboard I2C busses and FXOS8700 sensor Enable the onboard I2C busses and the FXO8700 sensor attached to I2C_3. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>	2019-04-22 08:40:03 -05:00
Henrik Brix Andersen	55502df866	boards: rv32m1_vega_ri5cy: add STS LED to DTS Add the status LED to the DTS of the RV32M1 Vegaboard RI5CY device tree. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>	2019-04-17 19:45:15 -05:00
Maureen Helm	d5351d8c3d	boards: rv32m1_vega: Fix red and blue led labels The red and blue led labels were swapped on the rv32m1_vega board. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>	2019-02-20 16:57:45 -06:00
Marti Bolivar	312ed45345	boards: riscv32: add rv32m1_vega This board directory supports the RV32M1 Vega board when targeting a RISC-V CPU core on the main SoC. Currently, only RI5CY support is provided via the rv32m1_vega_ri5cy board name. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>	2019-01-25 11:59:46 -05:00

5 Commits