Commit Graph

7 Commits

Author SHA1 Message Date
Gerard Marull-Paretas 0e69129fb3 soc: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:59 +02:00
Nazar Kazakov f483b1bc4c everywhere: fix typos
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
2022-03-18 13:24:08 -04:00
Daniel Leung 5d19da4507 soc: esp32: add support for GDB stub
This adds the SoC specific bits to enable GDB stub,
mainly the description for the register file, and
memory regions.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-11-30 15:24:00 -05:00
Anas Nashif a2fd7d70ec cleanup: include/: move misc/util.h to sys/util.h
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Leandro Pereira d3528cf001 soc: esp32: Update auto-generated _soc_inthandlers.h
Remove the auto-generated `handle_irq` label for the unneeded cases
to get rid of a compile warning.

Fixes #10801.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-10-27 21:25:57 -04:00
Leandro Pereira 7cea94942c soc: esp32: Use the smaller interrupt handling routines
Re-generate the ISR for ESP32, after modifying xtensa_intgen.py to
generate shorter code.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-10-22 13:38:29 -07:00
Anas Nashif cea0b3a9c2 xtensa: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00