riscv defines the machine-mode timer registers that are implemented
by the all riscv SOCs that follow the riscv privileged architecture
specification.
The timer registers implemented in riscv-qemu follow this specification.
To account for future riscv SOCs, reimplement the riscv_qemu_driver by
the riscv_machine_driver.
Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The qemu_riscv32 board makes use of:
1) the uart_riscv_qemu driver
2) the riscv_qemu_timer driver
Change-Id: I413e3990a66bc62a0d15d82ebca6940b381fed43
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Jean-Paul Etienne