Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
There are three types GD32 FMC.
GD32 FMC v1: its flash memory has 1 bank, page size is equal in the
bank, flash size is smaller than 512KB.
GD32 FMC v2: its flash memory has 2 banks. Page size equal within the
same bank but different between banks. Flash size can be up to 3072KB.
FMC v2 has two registers to control bank0 and bank1 separately.
GD32 FMC v3: its flash memory has 2 banks, use sector size as the
minimum operating unit, the sector size is not equal.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
Use the clock control API to enable peripheral clocks. Note that both
GPIO and pinctrl drivers are updated at once since they share some IP
blocks.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use the clock control API to turn on ADC clocks. Note that clock
selection is not yet implemented, so we still rely on custom rcu
properties for that.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new reset driver for GD32 platforms. This driver controls the
reset registers from the RCU peripheral. It can be used to restore
peripherals to their initial state when initializing a device.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add prescaler property to prevent counter driver imprecise when CPU clock
is close to the PIT clock.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
According to DT spec, device_type property is deprecated (ref. 0.3 spec,
2.3.11):
> The device_type property was used in IEEE 1275 to describe the device’s
FCode programming model. Because DTSpec does not have FCode, new use
of the property is deprecated, and it should be included only on cpu and
memory nodes for compatibility with IEEE 1275–derived devicetrees.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Make use of nodelabels to extend flash/sram nodes instead of re-defining
the whole tree. This pattern is already used in some other files.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
There's no need to specify the interrupt parent on each node, it can be
defined at soc level node instead (same as in ARM parts with NVIC).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Adding I2C FIFO mode can reduce the time between each byte to
improve the I2C bus clock stretching during I2C transaction.
The I2C master supports two 32-bytes FIFOs, channel A and C
are supported now.
I2C FIFO mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.
Test:
1. tests\drivers\i2c\i2c_api --> pass
2. Reading 16 bytes of data through i2c_burst_read() can reduce
0.52ms(2.4ms->1.88ms) compared to the original pio mode when the
frequency is 100KHz.
3. It is normal to read sensor data through I2C on Nereid's platform.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
All the of the ITE it8xxx2 devicetree compatiables are of the form
ite,it8xxx2-<DEV>. However the PECI device was ite,peci-it8xxx2,
rename the compatiable to match the pattern used everywhere else.
Signed-off-by: Kumar Gala <galak@kernel.org>
Some files were missed during the migration. This patch adds the prefix
where missing.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use the sifive,clint0 compatible instead of "riscv,clint0" and remove
interrupt controller fields (clint compatible is used for its timer
registers). Refer to the Linux or previous commits for more context.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use the sifive,clint0 compatible instead of "riscv,clint0" and remove
interrupt controller fields (clint compatible is used for its timer
registers). Refer to the Linux or previous commits for more context.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The CLINT (Core Local Interruptor) description was not aligned with
Linux. For example, there's no "riscv,clint0", but "sifive,clint0". The
peripheral is not described as an interrupt-controller either.
Ref. https://elixir.bootlin.com/linux/v5.18.14/source/arch/riscv/boot/
dts/starfive/jh7100.dtsi#L106
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
After some analysis I found out that there's no machine timer provided
by the "riscv" vendor. There are some specs for the mtime/mtimecmp
registers (this is why we can have a single driver), but the actual
register layout or implementations differ amongst vendors. GD32 uses the
Nuclei implementation, named "system timer" in their documentation. This
patch aligns with vendor specs.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Peter Marheine