Edited the index.rst file to say spi functionality is included. Also
edited the .yaml file in the boards directory to support spi for sanity
tests.
Signed-off-by: Jose Manuel Pacheco Luna <manuel.pacheco@nxp.com>
Added in enablement for the SPI-0 instance pins, as found in the
board schematic files. These connect to the arduino headers on the
front of the board.
Signed-off-by: Jose Manuel Pacheco Luna <manuel.pacheco@nxp.com>
Explicitly configures the rgb led pinmuxes as gpios. Currently the gpio
driver quietly changes the pinmux to gpio mode when configuring a gpio
pin, but this behavior is about to change.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Specific SW defined BLE LL parameters need to be set
if the user enables it on this platform. As such, conditionally
enable them directly into the defconfig.
INTMUX CH2 and CH3 are not available to be used if BT support
is enabled on Vega, because they are used internally by the
BLE SW LL
Signed-off-by: David Leach <david.leach@nxp.com>
Since the experimental BLE software link layer is enabled on
the VEGABoard, add some information about it, as well as the
limitations.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Having a pin toggle when the code reaches a certain point
is really useful for debugging; the infrastructure is already
in place for Nordic boards, so just build upon and enable the
mechanism on the Vega board as well.
Signed-off-by: David Leach <david.leach@nxp.com>
The board area was renamed from riscv32 to riscv back in July to
accommodate riscv64 support. Fix the remaining references in
documentation.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Enable the MX25R32 SPI NOR Flash on the VEGAboard and provide board
config file for the spi_flash sample.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
Same deal as in commit 7fdb525754 ("kconfig: Use 'default' instead of
'def_bool' in Kconfig.defconfig files"), but I hacked Kconfiglib to also
find cases where the type is given separately as e.g.
config FOO
int
default 3
Motivation (from a note in
https://docs.zephyrproject.org/latest/guides/kconfig/index.html):
For a symbol defined in multiple locations (e.g., in a
Kconfig.defconfig file in Zephyr), it is best to only give the
symbol type for the "base" definition of the symbol, and to use
'default' (instead of 'def_<type>' value) for the remaining
definitions. That way, if the base definition of the symbol is
removed, the symbol ends up without a type, which generates a
warning that points to the other definitions. That makes the extra
definitions easier to discover and remove.
It's also nice if 'def_bool' and the like turn into a semi-reliable flag
that the symbol is only defined in Kconfig.defconfig files. That might
be a sign that things could be cleaned up.
Will do a separate pass later to remove some symbols only defined in
Kconfig.defconfig files.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
We need to be able to specify GPIO flags in devicetree without that
preventing translation from the Arduino specifier to the host GPIO
specifier. Set up to ignore the low 6 bits of the flags field when
matching the child specifier, and to copy those bits to the parent
specifier.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
found some references to files (via :zephyr_file: and :zephyr-app:) that
were moved, so the links were broken
Fixes: #19660
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Update a number of boards that have arduino_gpio and arduino_i2c
support in their dts files to show that they support that in the
board.yaml file. This allows coverage on several shield tests that
utilize the tags 'arduino_gpio' and 'arduino_i2c'.
Exlucde stm32mp157c_dk2 from some of the samples right now since the
connector on the board doesn't support A2/A3. Also remove the duplicate
of exluding disco_l475_iot1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For OpenVega board, in the case of the Zero Riscy core,
the flash partition used for the code and data is the
M0 ARM core's 256KB flash region. This is closest to
the RISC core.
The m0_flash node defines where the interrupt vector
is located for the Zero Riscy core, and one needs to
restrict the application so its interrupt vector is
placed accordingly.
Fixes: 34b0516466 ("boards: riscv32: rv32m1_vega:
enable MCUboot for ri5cy core")
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Henrik Brix Andersen