Verify the thread priorities are within the bounds when starting a new
thread and when changing the priority of a thread.
Change-Id: I007b3b249e4b80235b6439cbee44cad2f31973bb
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
A race condition would happend if a FIRQ interrupted a
return-from-interrupt from a RIRQ at the wrong moment: if a decision was
already taken which thread to context switch in and the FIRQ woke up
another thread of higher priority, the ready queue would be corrupted.
The solution is to lock interrupts at the moment the interrupt return
code starts looking at the kernel queues. Interrupts do not need to be
unlocked before exiting: the return-from-interrupt (rtie) instruction
will restore the correct interrupt locking state for the thread being
context switched in.
Change-Id: I777665c2faeca7b1f2a77ddd9ee2a520080bae88
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The bitwise AND operator was being applied to the boolean expression
"!shared_data->flags" instead of the whole expression because a
parenthesis was lacking.
This bug has been found using Coccinelle using the following spatch,
after finding a similar bug somewhere else in the code base:
@@
expression E1;
expression E2;
@@
- !E1 & E2
+ !(E1 & E2)
No other instance of this defect has been found with this spatch.
Change-Id: I6b9ca092f4015c80ddc83c31ce540a92e67cdb11
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
An implementation to flush multiple d-cache lines has been added
per the top-level cache.h API. ZEP-1153 was opened to express
the need for MORE i-cache and d-cache APIs. For example, the current
cache.h API doesn't provide a means to invalidate d-cache lines
and has nothing for i-cache.
I've also modified some of the i-cache related aux registers to have
better names so that they won't be confused with d-cache.
These changes are for
ZEP-1176.
Change-Id: If4c5410451cc40dcd5618fc871093c8febf7e061
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Symbols now use the K_ prefix which is now standard for the
unified kernel. Legacy support for these symbols is retained
to allow existing applications to build successfully.
Change-Id: I3ff12c96f729b535eecc940502892cbaa52526b6
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
This KSDK flash shim driver supports the device in the FRDM K64F
platform (enabled with this commit).
WARNING: the driver disables the system interrupts for potentially
long periods of time. This is required to avoid Read-While-Write
issues since most platforms run in XIP mode.
For more detailed information see the link below:
http://cache.freescale.com/files/32bit/doc/app_note/AN4695.pdf
Change-Id: I70f8d09080251033ce2f45be0c2eb95c19fded08
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
The uart_k20 serial driver incorrectly assumed that all instances of the
UART peripheral are driven by the system clock, when actually some
instances are driven by the bus clock (which usually runs at half the
system clock). This caused incorrect baud rate calculations for UART
instances driven by the bus clock (UART2-4).
Change-Id: I38041781cdee146912bb5167e7c71d6416b966b5
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This change is required to support unified kernel.
Change-Id: I47bd644239eb3e624c7a5cb456eedad5aca79e8e
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
The unified kernel expect the default return value from a _Swap() call
to be set to -EAGAIN by the architecture code. Cortex-M3/M4 does this in
the SVC call handler, and it was missing from the Cortex-M0/M0+ before
pending PendSV.
Change-Id: I3316901186ab409f49043eb4f1972c4b0dd9a4a2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The pinmux configuration is done during board initialization.
This was validated using the following Zephyr apps:
- samples/hello_world
- samples/philosophers
- samples/drivers/uart
- samples/shell
UARTA0 is currently supported.
Change-Id: I85727c622d4d42183cc9f2f8b43d653e245dd17e
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Initial support is for the CC3200 SoC, comprising a network coprocessor
and Cortex-M4 MPU.
This leverages the CC3200 SDK driver peripheral library, installed
separately, or built from ext/hal/.
Jira: ZEP-1109
Change-Id: I508afc8596c165b309a4ec641c39abadc779eea3
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
The k64 SoC has multiple instances of many peripherals, but which
instances can actually be used depends upon the board design and pinmux
configuration.
Move all instance-specific default driver configurations from the SoC to
the boards (frdm_k64f and hexiwear_k64). Default driver selection
remains in the SoC (e.g., enable the KSDK I2C driver when I2C is
enabled).
This paves the way to support different driver defaults for the
frdm_k64f and hexiwear_k64 boards, but it does not yet change any of the
default values; it only changes where the default values get set.
Change-Id: Id9ed898762eb400ecefeac91ae4dce66da05622d
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds standard prefix to symbolic option that flags a thread
as essential to system operation.
Change-Id: Ia904a81ce343fdd1cd44caaaeae641d822777f9b
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
QMSI 1.3 natively supports restoring the SoC and peripherals
after sleep.
The Zephyr Power Management shim layer is updated
in order to support QMSI functions.
The following functions have been added:
void _sys_soc_set_power_state(enum power_state);
void _sys_soc_power_state_post_ops(void);
In order to fully support deep sleep, the function
_sys_soc_set_power_state now support saving and
restoring CPU context and returns to the application.
_sys_soc_set_power_state function also abstracts
QMSI cpu states and enable the application to choose
between C1/C2 or C2LP states.
The QMSI power states are mapped as follows:
SYS_SOC_POWER_STATE_CPU_LPS -> power_cpu_c2lp
SYS_SOC_POWER_STATE_CPU_LPS_1 -> power_cpu_c2
SYS_SOC_POWER_STATE_CPU_LPS_2 -> power_cpu_c1
SYS_SOC_POWER_STATE_DEEP_SLEEP -> power_soc_deep_sleep
SYS_SOC_POWER_STATE_DEEP_SLEEP_1 -> power_soc_sleep
The following functions have been removed:
void _sys_soc_set_power_policy(uint32_t pm_policy);
int _sys_soc_get_power_policy(void);
FUNC_NORETURN void _sys_soc_put_deep_sleep(void);
void _sys_soc_put_low_power_state(void);
void _sys_soc_deep_sleep_post_ops(void);
Those changes are propagated to the samples.
All calls to QMSI are removed.
Jira: ZEP-1045, ZEP-993, ZEP-1047
Change-Id: I26822727985b63be0a310cc3590a3e71b8e72c8c
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
A new shared memory has been added to the qmsi bootloader
in order to handle the restore flow and jump to
the restore trap where context is restored.
Add the new entry to the QUARK SE C1000 linker file
and new kconfig options:
- CONFIG_BSP_SHARED_RAM_ADDR to set the address of the
shared memory.
- CONFIG_BSP_SHARED_RAM_SIZE to set the size of the
shared memory.
This is only enabled with CONFIG_SYS_POWER_DEEP_SLEEP.
Jira: ZEP-1046
Change-Id: I35d924a100c5583025aa36a9741428ab51809c57
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Enable HAS_CUBE config flag on stm32f4 family soc.h is updated to
include minimum include files from ext/hal/stm23cube
Change-Id: I35a8c33aab777167ee7029edc1b7a4f6d21fccd8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Create HAS_CUBE config flag to control activation of STM32Cube support.
Generate fitting compilation options for STM32Cube in
/ext/hal/stm32cube/Makefile soc.h is updated to include minimum include
files from ext/hal/stm23cube
Change-Id: If58ce0a4fdb7fbf5f171dfe5f1f8eb75126a8313
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In ST CMSIS files, FLASH_BASE does not mean base address of FLASH register
Instead FLASH_R_BASE is used.
stm32f1 clock control driver is updated to be compatible with this naming.
Change-Id: Ic4fb49c60c392e15fd12c69266baf4c686bd343b
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32Cube uses SoC defines made to reflect HW heterogeneity that
should be taken into account by SW.
Aim of this commit is to adapt values used by Zephyr to the same
diversity. This will help create new SoC values only when justified
by a real hardware difference that should be taken into account
by software.
For instance, for SoC stm32f401re following define is used:
*STM32F401xE
Which means:
*Same SW could be used on STM32F401RE and STM32F401CE:
same CONFIG_SOC could be used
*Different SW should be used on STMF401RE and STM32F401RC:
different CONFIG_SOC should be used
This change focuses on stm32f4xx series.
Change-Id: I56ff4d1815d09747cf722385532eb2dcbdf37b44
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32Cube uses SoC defines made to reflect HW heterogeneity
that should be taken into account by SW.
Aim of this commit is to adapt values used by Zephyr to the same
diversity. This will help create new SoC values only when justified
by a real hardware difference that should be taken into account
by software.
For instance, for SoC stm32f103rb following define is used:
*STM32F103xB
Which means:
*Same SW could be used on STM32F103RB and STM32F103VB:
same CONFIG_SOC could be used
*Different SW should be used on STMF103RB and STM32F103R4:
different CONFIG_SOC should be used
This change focuses on stm32f1xx series.
Change-Id: I5ecfaa52952d04421b27b5e74fb71b4fc108b662
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The GPIO and AON GPIO ports are available to both the x86 and ARC
cores, but the driver always assumed only the x86 at the time of
configuring interrupts.
Use the available macros to set the correct values independently of
which core it's being built for.
Jira: ZEP-1030
Change-Id: I310afcc48780fbe1cac9dc3368a6de11bd797fda
Signed-off-by: Iván Briano <ivan.briano@intel.com>
The SoC level peripherals are accesible by both cores, while the SS
ones are only available to the sensor subsystem. Since the ARC core can
make use of both drivers at the same time, we need to be able to
differentiate their configuration values somehow.
Also disable the SoC GPIO for the ARC by default, as it still needs
more changes to be usable.
Jira: ZEP-1030
Change-Id: Ic5415c404ecd32a3e560467b6f5eaa873a515d72
Signed-off-by: Iván Briano <ivan.briano@intel.com>
IRQ numbers differ between x86 and ARC, as well as the bits that need to
be touched in the interrupt routing masks. QMSI abstracts some of it and
for the rest we do have the information needed.
Add a macro to select the right IRQ number based on which core we are
building for.
Change-Id: I3e6680d10a0a23c98777d2831efe6819fcb54162
Signed-off-by: Iván Briano <ivan.briano@intel.com>
There are a number of data sections that are repeated across
all the linker scripts for various architecture. In practice these
don't always get updated and we have had problems with bit-rot.
Consolidate these to make maintenance easier.
x86 linker scripts now follow the same naming convention and we
get rid of a linker-epilog.h that wasn't necessary and whose purpose
has been lost to the mists of time. If applications want to define their
own sections they should be allowed to. Linker scripts for x86 do not
end with .h any more, they are not C header files even though we use
C's preprocessor.
Issue: ZEP-688
Change-Id: I893eb4619969695c1f980efd7c2ec9fa5dad136d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We can derive NUM_REGULAR_IRQ_PRIO_LEVELS by subtracting 1
from CONFIG_IRQ_PRIO_LEVELS if FIRQ is present (which is currently
always the case). If FIRQ is not present, the value will be equal
to CONFIG_IRQ_PRIO_LEVELS since all interrupts will be regular.
Change-Id: Ibefc939e3771bf0adf712127db0d36cb49bf732b
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Update the QMSI drop we maintain in Zephyr, and fix the build where
needed:
- QM_SCSS_INT is renamed to QM_INTERRUPT_ROUTER;
- every member of QM_INTERRUPT_ROUTER was renamed as well;
- QM_IRQ_* renamed too, mostly added _INT at the end;
- some isr functions were renamed to keep their names consistent;
- build for x86 needs to define QM_LAKEMONT, as QM_SENSOR was for ARC.
Change-Id: I459029ca0d373f6c831e2bb8ebd52402a55994d1
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Move common config options one level up to try to simplify the per-board
defconfig
Change-Id: I3d80fa494050634d0f877af2015b01b85df20d1d
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for the STM32F401 chip on the board
Change-Id: I96c0799f3658ecea096fa5971bce9faf21919ee1
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
STM32F401 allows for upto 16 alternate functions on each pin.
Change-Id: Ib1c14fd31abaa2b05a5ab0f7bd1b4a4748f10f84
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Implements MCU-specific GPIO input interrupt integration. Added
definition of System configuration controller as well as its needed by
the GPIO code.
The SYSCFG controller is used for system-specific configuration such as:
- remap the type of memory accessible at address 0x00000000
- manage the external interrupt line connection to GPIOs
- configure the I/O compensation cell
Change-Id: Id2ebfbd1b21e77be76406d1cd6cd5d4989e9e2fa
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Based on the STM32F10x driver. Removing old code as we need to use the
bus number when dealing with 4 possible peripherals.
Change-Id: Id0263aa008e9b039ff9a00339e5622e289ffdf99
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds support for the STMicroelectronics STM32F4x family in the
STM32 MCU line. Configuration is included for the STM32F401RE MCU.
Acknowledgements to Pawel Wodnicki's earlier submission from February that
was used as a starting point for this port. In the end, we rewrote all of it.
Change-Id: I9797c282ac3c0cc66a63b9d34821de95df537ef6
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Fix the error in thread rescheduling:
Fix Fast IRQ exit routine error when it reschedules threads if
(prio >= 0) || (sched_locked == 0) || (next_thread == _current),
while the correct condition for thread rescheduling is:
(prio >= 0) && (sched_locked == 0) && (next_thread != _current),
Fix regular IRQ error when the regular IRQ exit routine rescheduled
threads when (next_thread == _current) instead of
(next_thread != current).
Increased IDLE_STACK_SIZE for ARC architecture, to hold saved
registers.
Change-Id: I1d87a968e231e13822844b7564567e6ca310cde2
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
The mk64f12 provides RNGA hardware. Follow the implementation pattern
used by various other driver classes and enable the RANDOM KSDK shim
driver if the RANDOM driver is enabled.
Change-Id: I46bdf16cf1c48937011fb1b0e4c292615efd4c95
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
They were the same, standardize on the lowercase one.
Change-Id: I8bca080e45f3e0970697d4451e468b9081f96f5f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
SOC_TI_LM3S6965 and UART_STELLARIS are platform-specific, remove from
arch/arm/defconfig.
Change-Id: I3b37bc2ddfabb1da4e7538b5ab0e553fb2464584
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
STM32F4 requires the alternative function config to be set, so just
initialize that as part of the gpio configure call.
Change-Id: I33a4a8efec59c5ebe7dc3f3580f0dd2bf7ded7f4
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Benjamin Walsh