XIP support in x86 was something of a mess. This
patch does the following:
- Generic ia32 SOC no longer defines a "flash" region
as generic X86 devices don't have a microcontroller-
like concept of flash. The same has been done for apollo_lake.
- Generic ia32 and apollo_lake SOCs starts memory at 1MB.
- Generic ia32 SOC may optionally have CONFIG_XIP enabled.
The board definition must provide a flash region definition
that gets exposed as DT_PHYS_LOAD_ADDR.
- Fixed definitions for RAM/ROM source addresses in ia32's
linker.ld when XIP is turned off.
- Support for enabling XIP on apollo_lake SOC removed, there's
no use-case.
- acrn and gpmrb boards have flash and XIP related definitions
removed.
- qemu_x86 has a fake flash region added, immediately after system
RAM, for use when XIP is enabled. This used to be in the ia32 SOC.
However, the default for qemu_x86 is to now have XIP disabled.
- Fixed tests/kernel/xip to run by default on boards that enable
XIP by default, plus an additional test to exercise XIP on
qemu_x86 (which supports it but has XIP switched off by default)
The overall effect of this patch is to:
- Remove XIP configuration for SOC/boards where it does not make
any sense to have it
- Support testing XIP on qemu_x86 via tests/kernel/xip, but leave
it off by default for other tests, to ensure it doesn't bit-rot
and that the system works in both scenarios.
- XIP remains an available feature for boards that need it.
Fixes: #18956
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Since Kconfig is responsible for enabling/disabling devices at build,
the devices in dt are defaulted to status="ok" to keep the output in
generated_dts_board.conf the same across configurations and simplify
the board-level dts files.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
I2C support has been added back into the up_squared, leveraging the
new PCIe support in the DesignWare I2C driver.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This needs to be pushed down to the SoC level, as it's an Apollo Lake
feature, not a feature of the UpSquared. Remove the Apollo Lake
references to the PCI devices because these will not be used when I2C
support is restored.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The UARTs are on the SoC, not the board, so move their descriptors
to the SoC-level. Also turn on auto IRQ detection as these are PCI-
attached and their IRQs are subject to change depending upon firmware
settings.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A new function pcie_irq_enable() is added to be used in lieu of
irq_enable() when the target device is PCI(e)-attached. The function
attempts to use MSI, when configured in the kernel and supported by
the endpoint; failing that, it will verify that IRQ requested is in
fact routed to the device by the boot firmware before enabling it.
The NS16550 UART driver is updated to use pcie_irq_enable().
The PCI(e) shell is extended to dump information about wired IRQs.
The up_squared devicetree is fixed (reverted?) to IRQ5 for UART1.
The galileo enables MSI by default.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Removed Console dependencies from shell uart backend.
Generated define: CONFIG_UART_SHELL_ON_DEV_NAME for each board.
Fixes#10191
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
Fix the following dts warnings:
up_squared.dts_compiled: Warning (simple_bus_reg): /soc/gpio@0:
simple-bus unit address format error, expected "d0c50000"
up_squared.dts_compiled: Warning (simple_bus_reg): /soc/i2c@91528000:
simple-bus unit address format error, expected "9158000"
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we have a common DT_SIZE_K macro use it instead of defining
__SIZE_K eveywhere. We also have DT_SIZE_M, so use that in a few
places as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add the necessary bits to enable the I2C controllers on
the UP Squared board. Only the ones exposed through the HAT
connector(s) are enabled by default.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a primitive board configuration for the UP Squared board
containing Apollo Lake based Pentinum and Celeron SoC. This has
been tested on model UPS-APLP4-A10-0432.
This starts from the minnowboard configuration, and document
from galileo.
Origin: Original
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Andrew Boie