XIP support in x86 was something of a mess. This
patch does the following:
- Generic ia32 SOC no longer defines a "flash" region
as generic X86 devices don't have a microcontroller-
like concept of flash. The same has been done for apollo_lake.
- Generic ia32 and apollo_lake SOCs starts memory at 1MB.
- Generic ia32 SOC may optionally have CONFIG_XIP enabled.
The board definition must provide a flash region definition
that gets exposed as DT_PHYS_LOAD_ADDR.
- Fixed definitions for RAM/ROM source addresses in ia32's
linker.ld when XIP is turned off.
- Support for enabling XIP on apollo_lake SOC removed, there's
no use-case.
- acrn and gpmrb boards have flash and XIP related definitions
removed.
- qemu_x86 has a fake flash region added, immediately after system
RAM, for use when XIP is enabled. This used to be in the ia32 SOC.
However, the default for qemu_x86 is to now have XIP disabled.
- Fixed tests/kernel/xip to run by default on boards that enable
XIP by default, plus an additional test to exercise XIP on
qemu_x86 (which supports it but has XIP switched off by default)
The overall effect of this patch is to:
- Remove XIP configuration for SOC/boards where it does not make
any sense to have it
- Support testing XIP on qemu_x86 via tests/kernel/xip, but leave
it off by default for other tests, to ensure it doesn't bit-rot
and that the system works in both scenarios.
- XIP remains an available feature for boards that need it.
Fixes: #18956
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The '#if XIP' in the DTS file never worked properly,
causing the QEMU build to think it has much more RAM
then it actually has. If RAM overflowed, this would not
be caught by the build, instead there would be strange
crashes when the data copy takes place.
The QEMU targets themselves are not XIP, everything
is actually RAM, but the first 4 megabytes are
considered to be a memory-mapped flash region. This
is done to ensure that the XIP data copying infrastructure
doesn't bit-rot on x86. We are at the point where
a lot of things depend on this, so just select it in
the board Kconfig instead of enabling in the
defconfigs.
Fixes: #15835
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Maybe this is some "just in case" thing that got copied around. There's
no need to have a blank line at the beginning or end of Kconfig files.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This build target is intended to verify that enabling the
IAMCU ABI doesn't have any bit-rot since we can easily
run this under emulation.
However, the QEMU boards all derive from the generic IA32
SOC definition, which is any pc-like hardware. We need
to disable these mitigations for this target since the
IAMCU compiler doesn't even recognize instructions like
'lfence'.
Fixes: #14315
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Not all boards can get the coverage reports. The report generation
needs minimum of 64KB SRAM. This patch added support for mps2_an385,
qemu_cortex_m3, qemu_x86. This is just a subset. Also the previously
supported board native_posix is included in this patch.
If a board has 64KB RAM, it can generate reports by just
adding HAS_COVERAGE_SUPPORT in Kconfig.board.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Remove either duplicate settings between arch & board, or just set
HAS_DTS at the arch level since all the boards for a given arch support
DTS now.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This will be usefull to tell when Ethernet device has its attributes
filled in by DTS rather than by Kconfig.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Getting warnings from Kconfig after generalising how CPU_HAS_FPU is
configured on the architecture level. 2 Boards were settings this value
in the wrong place.
Fixes#5211.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This will allow checking if we are building for QEMU globally, without
having to know the exact architecture and board name.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduce an architecture sorting of boards. This is to allow for
easier maintenance going forward as the number of boards grows. It
will be easier for any scripts to know the board/arch mapping without
having to maintain an explicit list of what boards are associated with
which arch. We can also do things like have architecture maintainers
cover reviews and branches for arch/${ARCH} and boards/${ARCH} going
forward.
Change-Id: I02e0a30292b31fad58fb5dfab2682ad1c5a7d5a7
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Andrew Boie