Commit Graph

624 Commits

Author SHA1 Message Date
Anas Nashif c3a7fd2844 arm: use wildcards for kconfig
Move platform related data and definition to the platform
directory and include it using:

arch/<arch>/platforms/*/Kconfig.platform

This way we will able to add a platform as a directory of
content without the need to change and Kconfig files.
Platforms can then be included by reference (using repo or
git submodoules)

Change-Id: I6bff4e48490e33cbaf879fe3c424bf2f6a4887ac
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif cd158f3750 x86: only build configured platform
Do not reference every platform, instead use the platform
name to tell make what to build.

Change-Id: I7498da7cdcdada754466222902f59fe4c6487d89
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif a4266c3baf kconfig: use wildcards for platforms
Move platform related data and definition to the platform
directory and include it using:

arch/<arch>/platforms/*/Kconfig.platform

This way we will able to add a platform as a directory of
content without the need to change and Kconfig files.
Platforms can then be included by reference (using repo or
git submodules and does not need to be part of the zephyr
project)

Change-Id: I5e71f5394c22edb346f7d61d9448b8e1c68e1f9b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Tomasz Bursztyka 39621510e2 Kconfig: quark_se-x86: Set proper default config settings
Provide the proper irq for i2c, gpio and spi. And make relevant drivers
getting enabled easily once their domain is selected.

Change-Id: Ib8a428e11b6163a1b370b23baa34ea2fab733565
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:52 -05:00
Tomasz Bursztyka 49ea925727 quark_se-x86: Provide the i2c IRQ flags
Without that, it won't built when enabling support for dw i2c in
quark_se-x86.

Change-Id: Icce26488d870c273516dc9f34555176122bcb9c8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:52 -05:00
Tomasz Bursztyka 14267b85c9 spi: dw: Fix various building and support issues
- Build the actual driver when relevant
- Provide the IOAPIC stub
- Provide the IRQ flags for IRQ_CONNECT_STATIC
- Set the default IRQ priorities

Change-Id: Iea20ef67c92cf7f48791fba5a8021448b7059950
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:52 -05:00
Szymon Janc c0baad2262 Rename simple UART driver to pipe UART
Original name was too generic and confusing. This patch renames
driver to pipe UART and moves it to console drivers folder. Kconfig
destription is also improved.

Change-Id: I716fdbf7d636bbdc03b0fce27a59fd866f473246
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
2016-02-05 20:24:52 -05:00
Anas Nashif 42d94e5dbe x86: Add Quark D2000 platform with nanokernel support
The Intel Quark microcontroller D2000, is a low power, battery-operated,
32-bit microcontroller.  Within its small footprint, the Intel Quark
microcontroller D2000 includes an Intel Quark ultra-low-power core
running at 32 MHz, with 32k integrated flash and 8k OTP SRAM.

Change-Id: I6ba121996edb0b5fbe596bd6ef3d6e3979ff73e9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:49 -05:00
Anas Nashif 00c4d32d42 x86: add Quark D2000 Interrupt Controller (MVIC)
This module is based on the standard Local APIC and IO APIC source modules.

This modules combines these modules into one source module that exports the
same APIs defined by the Local APIC and IO APIC header modules. These
routine have been adapted for the Quark D2000 Interrupt Controller which has
a cutdown implementation of the Local APIC & IO APIC register sets.

Change-Id: Ic80aa78918483663d76054ebadefa08d8a3f188a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif b0b936b51c arc: add Quark SE Sensor Subsystem nanokernel support
Change-Id: I8178076e9f8bf98c3149f3622aa2236070446c62
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif 28af1ee421 Move RAM and NSIM option to architecture level
Change-Id: Ic47e263bebe4bc2fecb233856ddd1f5de85c11d8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif 226404c4bf x86: go back to integers for ram/rom size
This cause problems with some configurations using hex.

Change-Id: I680c40d46e1fdf3da714f6412c8dda0e1ebb44f9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif 4a4de7069e x86: add support for the Quark SE platform
Intel Quark SE Microcontroller with an onboard sensor subsystem.

Processor
* Intel Quark SE Processor Core
* Intel Pentium® Processor-based x86 ISA compatible CPU
* 32MHz clock, 32-bit address bus
* 8kB 2-way L1 instruction cache
Memory
* 384kB of on-die NVM +8kB OTP on-die NVM
* 80kB of on-die SRAM

Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif 98beac134e add physical RAM address variable
Keep things consistent across all platforms and make this
configurable and avoid hardcoding in linker.cmd file.

Change-Id: Iddeb5107854139249fda70378e07b83066d8a7a1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Daniel Leung d3d64ca4cf bluetooth/uart: register driver at boot if enabled
The driver should handle the initialization instead of relying on
platform initialization. This is to conform to the driver model.

Change-Id: Idc95d59bce2470b5118e416ee05f07548991a15c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:48 -05:00
Dmitriy Korovkin 470ce8482c Initialize UART irq number statically
When PCI bus is not enumerated, I/O memory and IRQ
numbers need to be statically initialized.

Change-Id: I4efcccd95d8048910f6c900c8daf46cbe3a5fa00
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:24:48 -05:00
Andrew Boie f6dd6d5fd8 x86: atomic: don't use '__asm__ goto'
Not supported in LLVM/clang.  As it turns out,
this new implementation is 4 bytes shorter than its
predecessor.

Change-Id: I1f63b7a245dafcfc5a6dadc293875f00d02b997c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:47 -05:00
Anas Nashif db26a98c93 Fixed various clang build issues
Fix a few spots where building with with clang fails.

Change-Id: I621c7cb8daf119bf89ad512168d70e1c9b67e53f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:47 -05:00
Anas Nashif 1b702154b5 kbuild: add clang support
Clang support already existed in the Makefiles but was not complete
and some gcc options did not work with clang. Move those to be conditional
on the compiler used to make clang work.

To build with clang for x86:

make  CC=clang  -C samples/microkernel/apps/hello_world/

You still need the gcc cross environment for various tools.

For now, only x86 was tested.

Change-Id: Ic5aeab4f80d312e1d1312a4a9fc885a43f760270
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:47 -05:00
Dmitriy Korovkin f1420515a7 irq: Add flags to IRQ_CONNECT_STATIC() macro and irq_connect() function
Flags allow passing IRQ triggering option for x86 architecture.
Each platform defines flags for a particular device and then
device driver uses them when registers the interrupt handler.

The change in API means that device drivers and sample
applications need to use the new API.

IRQ triggering configuration is now handled by device drivers
by using flags passed to interrupt registering API:
IRQ_CONNECT_STATIC() or irq_connect()

Change-Id: Ibc4312ea2b4032a2efc5b913c6389f780a2a11d1
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:24:44 -05:00
Tomasz Bursztyka 74e29ac373 galileo: Use SCH GPIO driver for it's legacy bridge GPIO controller
Such controller offers 2 blocks (respectivelly Core Well and Resume
Well) on Quark x1000, with 2 and 6 GPIO pins to use.

Change-Id: I50075f0880bef4574e9eeb1c65602082e8da647a
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:44 -05:00
Anas Nashif 6ba5c09d23 kconfig: change RAM_SIZE to be in hex
We already had this kconfig defined as hex for arc. Make it
readable and change the variable to hex to comply with what
we had already.

Change-Id: Ib8bc72f27d1b97ba2c886201ec29fb13aa4fa429
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:43 -05:00
Anas Nashif c5ad109c7b fsl_frdm_k64f: do not declare kernel type
This is done from the kernel fragments, no need to declare it here.
(micro kernel is the default anyways)

Change-Id: I88511c03f44538cab3e8fbf8292e179e01005b0d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:43 -05:00
Anas Nashif a3f8d81614 cortex_m: re-add __start definition for cortex_m
This was removed as part of some Diab cleanup, however it is needed
and without the definition we get the following when building
for the FRDM-K64F  board:

arm-none-eabi-ld: warning: cannot find entry symbol __start; not setting start address

Change-Id: Ie0604a600b6f7a4faa321c58aa63c5617a163107
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:43 -05:00
Andrew Boie c065ed5d78 x86: reduce footprint of exception debugging
We're smart, we can look up the vector IDs in a book if we
don't already know what they are.

Change-Id: Iaff3986d7c96dea597be4b2a5b13721ab57980fa
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:43 -05:00
Vlad Lungu 3fc0f0f422 fsl_frdm_k64f: Increased NUM_IRQS to 86
Needed for the Ethernet MAC

Change-Id: Iecef5be818c87c34280ea32123f05b8f5974a998
Signed-off-by: Vlad Lungu <vlad.lungu@windriver.com>
2016-02-05 20:24:43 -05:00
Benjamin Walsh 665dd5d331 galileo: disable SPI_PORT_1 by default
Unused, uses IRQ17, which conflicts with UART1.

Change-Id: I5d285ee8a2e7e5d45b38a85a417bd36f0e4bb92e
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:43 -05:00
Dmitriy Korovkin ea5ff12110 galileo: Add ADC configuration
Change-Id: I694d2812496220e54e757cb89ce0c529f3bad48f
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:24:43 -05:00
Peter Mitsis c7a76a226d galileo: Fix SPI speed and configuration values
Change-Id: If15b2931e00d3a5748a56cea673e694389a7e963
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:43 -05:00
Peter Mitsis c5b10c6006 x86: Display registers on fatal error
Change-Id: Idb05fbb707f2c95173423c928acda2a07e962989
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:43 -05:00
Peter Mitsis 6338c4518c x86: Update NANO_ESF and NANO_ISF structures
As the system always operates in ring 0, neither the SS nor ESP registers
are pushed onto the stack when an exception or an interrupt occurs.
However, as the ESP field is still relevant to debugging fatal errors, a
place has been carved for it in the NANO_ESF.

Change-Id: Ibb2578c69fa6365fd6e9dbf7b51f461063dadc68
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:43 -05:00
Peter Mitsis e7018455d8 x86: Remove cr2 field from NANO_ESF structure
As page fault exceptions can not occur in the system as it is currently
designed, there is no need to track the CR2 register as part of the
exception stack frame.

Change-Id: I75d7a74c5d2c6efcc0e9141d2662861bc2052629
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:43 -05:00
Benjamin Walsh b0edae6047 x86/qemu: do not use -no-reboot flag when REBOOT=y
The -no-reboot flag causes QEMU to exit when trying to reboot through
the RST_CNT register.

Change-Id: I01262753587d2fc4e787262a8368ddba39fdeaa1
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:43 -05:00
Benjamin Walsh f9127ecf52 reboot: add support for galileo
Implementation of the sys_arch_reboot() call for galileo, using the
RST_CNT register (I/O port 0xcf9).

Change-Id: I00fbf4aaaf746f640674da6880e1d6c5aa230e06
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:43 -05:00
Benjamin Walsh 3ab75623fa x86: add kconfig options for RAM/ROM size
CONFIG_RAM_SIZE
	CONFIG_ROM_SIZE

Available to x86 based platform configurations.

Change-Id: I3dda770a9063e3c717023b1a83761f32caa2c590
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:42 -05:00
Peter Mitsis 3e06e7293f arc-linker scripts: Add _image_[ram|rom]_[start|end] symbols
Adds the following standard symbols to the arc linker scripts:
	_image_rom_start
	_image_rom_end
	_image_ram_start
	_image_ram_end

Change-Id: Ib1dfa1dcb85140193557e72536145e74eb3ebb91
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:42 -05:00
Peter Mitsis abc1694614 arc-linker scripts: Replace __text_start/end symbols
Standardizes on using symbol names _image_text_start and
_image_text_end instead of __text_start and __text_end.

Change-Id: I160ed6b4f117483fcffdfa04ce10bd6a5151704a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:42 -05:00
Andrew Boie 05d6c92621 x86: cpuhalt: rewrite using inline assembly
Eliminates issues with compilers that have different C calling
conventions.

Change-Id: I9318edd5eea6b6bacdf3da2c28e0e29315d5cdf5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:42 -05:00
Andrew Boie 033ee894b9 x86: use GCC inline asm for MSR read/write
Eliminates issues with compilers that expect different C
calling conventions.

Change-Id: Ic70a15926380671a7b9c058b53400b10b5c870a7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:42 -05:00
Andrew Boie 6bf328b6ea x86: use GCC inline assembly for atomic operations
This doesn't make any assumptions on calling conventions or
the structure of the stack, and should thus be portable to
compilers that implement different C calling conventions.

In order for the rewritten functions to take up the same code
size as the pure-asm counterparts, -fomit-frame-pointer has
been specified for each of them, otherwise an extra 4 bytes
is used for every function.

The generated assembly code by these new functions has been
verified in GDB to be the same as the old ones, except a few
trivial things like particular registers used.

Change-Id: I9a896cbfc3e7f4c2497d749140729d28b32f1c9d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:42 -05:00
Andrew Boie 30f01d86e0 x86: remove CONFIG_LOCK_INSTRUCTION_UNSUPPORTED
This was only needed on legacy platforms which are no longer
supported.

Change-Id: I4a3312f3698c4fc8bbf0df4610af7b69a9056f80
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:42 -05:00
Andrew Boie 8a2104e16a x86: remove CONFIG_UNALIGNED_WRITE_UNSUPPORTED
This had bit-rotted to the point where it was breaking the build
and was only needed on legacy platforms that are no longer
supported.

Change-Id: I4fcfc38bacac58761fba475701e0c27d7b8b7a27
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:42 -05:00
Anas Nashif 6de1c20809 core: remove NO_ISRS feature
This option is not building and currently not supported, removing
it because there does not seem to be a use case for it.

Change-Id: Idb8ffedf83f43cffc68a01573c6f2d1a90fc40fb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:42 -05:00
Anas Nashif 14cb8da750 Revert "kbuild: add clang support"
This reverts commit 58fd0778c6dcc6bd3148b5d07615cd7bd777f456.

Change-Id: Ibffe036d2e182652b3c966c10ed405c9386f823c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:42 -05:00
Andrew Boie b43758d22a x86: remove dynamically generated IRQ and exception code
We are interested in supporting some XIP x86 platforms which are
unable to fetch CPU instructions from system RAM. This requires
refactoring our dynamic IRQ/exc code which currently synthesizes
assembly language instructions to create IRQ stubs on-the-fly.

Instead, a new approach is taken. Given that the configuration at
build time specifies the number of required stubs, use this
to generate a build time a set of tiny stub functions which simply
push a 'stub id' and then call common dynamic interrupt code.
The handler function and handler argument is saved in a table keyed by
this stub id.

CONFIG_EOI_HANDLER_SUPPORTED removed, the code hasn't been conditionally
compiled for some time and in all cases we call _loapic_eoi() when
finished with an interrupt.

Some other out-of-date verbiage in comments related to supporting
non-APIC removed.

Previously, when dynamic exceptions were created a pointer would
be passed in by the caller reserving ram for the stub code. Since
this is no longer feasible, two new Kconfig options have been added.
CONFIG_NUM_DYNAMIC_EXC_STUBS and CONFIG_NUM_DYNAMIC_EXC_NO_ERR_STUBS
control how many stubs are created for exceptions that push
an error code, and no error code, respectively.

SW Interrupts are no longer triggered by "int <vector>" hard-coded
assembly instructions. Instead this is done by sending a self-directed
inter-processor interrupt from the LOAPIC, using a new API
loapic_int_vect_trigger(). In this way we get rid of dynamically
generated code in irq_test_common.h.

All interrupts call _loapic_eoi() when finished, since this is now
the right thing to do for all IRQs, including SW interrupts.

_irq_handler_set() for x86 no longer requires the old function pointer
to be supplied.

Change-Id: I78993d3d00dd153c9051c518b417cce8d3acee9e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:41 -05:00
Anas Nashif 0d0cb8e661 kbuild: add clang support
Clang support already existed in the Makefiles but was not complete
and some gcc options did not work with clang. Move those to be conditional
on the compiler used to make clang work.

To build with clang for x86:

make  CC=clang  -C samples/microkernel/apps/hello_world/

You still need the gcc cross environment for various tools.

For now, only x86 was tested.

Change-Id: I1a50c3a82d79ff3001beb4366961ca810eeb6006
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:41 -05:00
Yonattan Louise e378747706 Rename Profiler to Event Logger.
In order to have a name according to the functionality of the feature.
This commit rename any text, function and variable related with the
Profiler name to Event logger.

Change-Id: I4f612cbc7c37965c35a64f06cc3ce5e3249d90e5
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:24:41 -05:00
Benjamin Walsh 334c14e66e x86: CLFLUSH and cache line size detection
Detect the presence of CLFLUSH instruction and cache line size at
runtime. It is still possible to set them manually via kconfig options
if the values are known.

Change-Id: I00bda1de4c5c241826ead6f43b887b99a963cc7b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:41 -05:00
Benjamin Walsh aed578cb03 x86/cache: rename _SysCacheFlush to sys_cache_flush
Change-Id: Idb1bbedea9577856ea6db08683ea4a4ead92e14d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:41 -05:00
Benjamin Walsh b7875a0bc8 x86: Rename PHYS_ADDR/VIRT_ADDR to paddr_t/vaddr_t
Change-Id: I8e037278f2f1d409360c52276cb4dae87b9ad440
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:41 -05:00