Change all the Intel and Wind River code license from BSD-3 to Apache 2.
Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
It's an SPI driven chip and proposes up to 8 channels for input
conversion. It's found on Galileo board.
Change-Id: I916367e9be0849812c6a509082a501730a01ce60
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It might be needed sometime to get some private data forwarded to the
callback, thus such user_data pointer is the easiest way to proceed.
Adding a macro to set the word size as well.
Change-Id: I68cbe2d480120253ccb13f13c656a38c27e21604
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
If those are not set it means the controller has nothing to request
anymore from the driver.
Change-Id: Ie7e834e82b931e4b02ded3f9f619735b31b0a121
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Since the driver is the only one needing those, no need to expose them
anywhere.
Change-Id: Iac4eaa65a9dbdaa8e72c70ea0de35cd2b3d836d1
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
At this points the slave is ready to deal with the master.
Change-Id: I815d3c577bd0b73100cbf585cc8ca78f180ec713
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This was failing, the documentationg provides numbers only telling at
one places these are hexadecimal values. So switching to hexadecimal.
Then DDS rate retrieving macro was bogus, so fixing it.
And adding debug output about the DDS rate and the clock ratio.
Change-Id: I9cc414796fbd7f7123f1f406c6bce7ffacf641e8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
With the introduction of generic transfer function, it is no longer
needed to specify read or write functions explicitly in drivers.
All read/write functions can now thus call the generic transfer
function to achieve the same result.
With this change, the transfer function becomes mandatory, and
should always be available.
Change-Id: Ia6fb98e58b84330a56a5d44ed3df9db42c3a5e88
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The newly introduced i2c_poll_transfer() is now used for register
read for PCAL9535A GPIO driver. The old write then read does not
work because every read or write ends with STOP. However,
the chip requires RESTART after writing the register address.
So the new generic transfer function is perfect for this.
Change-Id: I56d7ebe08f68cb04731c72138d60645ef124f65e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() For interrupt driven transfer, the driver already has
a generic transfer function, so this simply exposes it
for public consumption.
() The polling write is extended to support generic
transfer.
Change-Id: I657db8a6376282c723728b7a875813d389cf7d27
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Re-organize the steps involved in data transfer, according to
the datasheet's flowchart.
() Extract the common code for transfer initialization and put
it into its own function.
() i2c_write() and i2c_polling_write() are now using the common
data sending function.
Change-Id: Ieb90253ee10ddceb3b5d05b258e7fc6253d18729
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Both poll_in and poll_out are supposed to be implemented
in each driver, as these are basic function.
Change-Id: If1b6b11834f57934fe7e776bfcf818e088abdd0a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
PCI legacy bridge is a device connected to PCI bus and
allowing to program the routes from interrupt pins to IRQ
numbers.
Change-Id: I129719d71f958bbf5ad8c5c9949dcea93d94b89d
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
PCI enumeration is not mandatory to enable as static information can be
provided. Plus, it does not integrate yet properly with shared IRQ as
well as setting dedicated IOAPIC paremeter for certain drivers.
Change-Id: I221b2a8a2179993a264e5f3eb93cda0e121d9abe
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Providing the right settings through Galileo's Kconfig.
Change-Id: Ia5339eb90cb98d7dde3be0493bcfd9a6b6db60ed
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add Kconfig option to specify how interrupt is triggered for SPI.
Also enabling such support for Galileo platform.
Change-Id: Id3112d100089197940f826b827493174d0f22669
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This is specific to Galileo board where its SPI port 0 needs to setup
the CS pin through a GPIO pin.
Change-Id: I9df6f7144a96bcd10f61fc7d057f89caa0e599d1
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Fix previous rebasing errors (before merging) where deleted code
was reintroduced back. This causes the default configuration
in Kconfig to be ignored.
Change-Id: I29b246b1459136521d764127bf02e6d8e5aff30c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This expands the Galileo pinmux driver to configure the GPIOs
on the DesignWare IP block, and the core/resume wells on
the legacy bridge.
Change-Id: Ia1df4b6fd3b104f08563fe9eab93f01efbb53b66
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
If using with shared IRQ, this function will be called by
the shared IRQ driver. So we need to check and bail out
early if the interrupt is not coming from the GPIO
controller.
Change-Id: I4ae925f5fb9a5c32d03a180edc8460e978ec0aac
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
If using with shared IRQ, this function will be called by
the shared IRQ driver. So we need to check and bail out
early if the interrupt is not coming from the I2C controller.
Change-Id: I3c3ae3c22aa5cf312de5c22b35765749d6c5929d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Such settings belong to Galileo and thus are set in Galileo Kconfig.
Change-Id: Ib9ec721fcc68e92521f8b7690c2640eeb82b2f4c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Call the callback when relevant:
- When STOP_DET if received
- On error
Change-Id: Id60190c6ac5c0b15a0a6cd3fb30b9cc41f2333e8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Handle only the pins which have been configured to be present on this
controller. Removing an unused #define as well.
Change-Id: I66d3638333f1fcd49b1b4f70a5c9d11dbc538fd0
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On some platforms (e.g. Galileo), the I2C controller is on PCI bus,
which shares IRQ with other devices (GPIO on Galileo). This patch
adds support for utilizing shared IRQ.
Change-Id: Id4e4714aed37c2893d0ffe9ed1e4edaabb338121
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
On some platforms (e.g. Galileo), the GPIO controller is on PCI bus,
which shares IRQ with other devices (I2C on Galileo). This patch
adds support for utilizing shared IRQ.
Change-Id: I4b44bae15356e4710d54f0343fed1bd27f35e484
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds options to the shared IRQ driver so the interrupt
triggering condition can be specified.
For example, the GPIO and I2C controllers are under same
interrupt line through PCI bus. The triggering condition
is level, active-low. So this option can be used by
the Galileo platform to program the IO-APIC correctly.
Change-Id: I1c3af98442e775b4987ab36a644c856052d85ec4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This driver allows multiple drivers to share a common interrupt
line. This functionality is required on system that conform to the PC
interrupt structure. In the context of Zephyr this is needed for
SOC's that have their I/O IP blocks behind a PCI interface. Due to the
limited number of interrupt lines provided by the PCI interface
multiple IP blocks may be configured to share an interrupt line.
Drivers that share interrupts must be modified to *not* register their
own interrupt service routine as part of their configuration/initialization
but instead bind to the correct instance of this driver by name, then
register their interrupt service routine with this driver.
Change-Id: I57b517b97ebeabce484ba53c8f940da993cb391d
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
The polling I2C write function guarantees the write operation
is completed. It is to make sure each write has been commited.
Change-Id: I37cd3b8a65c605837b1fae3ccd1c2b0235c07a37
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The polling I2C write function guarantees the write operation
is completed. Given that the initialization routine goes through
I2C write consecutively, we want to make sure each write
has been committed.
Also adds code to configure the I2C controller before transfer.
Change-Id: I2c8888e940edd1cb9fb01f03234a731ac991dfcf
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This implementation will wait to write, and wait for transfer
to complete before returning from the function. Currently has
a default timeout of 100ms to prevent being stuck in the loop
waiting for hardware to be ready.
Change-Id: I0340fc6fed100f1d31c0306c5b0ab09689364f63
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add I/O port access to MMIO-based GPIO driver, in addition to
the existing direct memory access. This extends the driver,
so that it can address the registers through I/O read/write.
Change-Id: I53c74ad76472ac043764e33bfbb77a2bedc427fe
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The interrupt selectionss are no longer specific to a particular
controller (e.g. I2C_DW_0), but apply to all controllers on
the platform.
[DL: Extracted these changes into their own patch, instead of
being squashed with others. Also modified the Kconfig
options to move them into proper position.]
Change-Id: Idc7ac9769e947447b868dccf772a95dbb5fc8021
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Add a Kconfig option to enable NANO_TIMERS for PCAL9535A.
Without enabling nano timers, compilation may fail.
Change-Id: If96358a17b9522f9323f3480b4716c3dfd82a3de
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The I2C controller should have been already setup before this driver.
Since the only use right now is on Gelileo and I2C_DW driver. it is
safe to remove the i2c_configure() call now as the driver has default
configuration at boot.
Change-Id: Ia384e28871bf76dcfec899860f93da4bf0948ba6
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the Kconfig option to specify default configuration
for the I2C controller during driver initialization.
During boot, the controller needs to be configured before
communication to slave devices can start. After boot,
an app can re-configure the controller if needed.
Change-Id: I7bf252f75a31943ae444e4d914f3a9a1a3f3d91f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are devices that need are part of the architecture core the need
to be initialized prior to devices that are integrated around a core
to make up a complete SOC. Namely the interrupt controller in the SOC
must be configured in order to allow the integrated IP blocks drivers
to initialize correctly.
Change-Id: I0a91e08f98516a7b7dd402ffc6494a071f1326b2
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
This macro is legacy from an early implementation of the init system
before the pure level was split into early and late phases remove it
now to avoid confusion going forward.
Change-Id: I6720874c840c9e14888fd6f411a8182e7420ca29
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
This provides the API to manipulte the pin muxing, where
a single pin may provide different functions depending on
settings.
[DL: changed commit message.]
Change-Id: Ifd161137c062dff184024b5aa34737604911d09c
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the driver for PCA9685 I2C-based PWM chip, and provides
basic PWM functionality.
Change-Id: I8c711d9b703fdaf5ccb23657e07495a95cbe16ee
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fixes a build failure in designware gpio driver.
Change-Id: I90a540f56bff17ff56d0315356fde6d6c4d02407
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Javier B Perez Hernandez