Add device tree elements for all gpio ports of the efr32mg12p including
the dts fixup entries.
Also remove gpio port e since this is not available in efr32mg12p socs.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
NXP's LPC family of MCU's GPIOs parameters is udated.
Boards LPC54xxx and LPC55xxx have updated values according
pin and interrupt layout.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This commit adds basic support for nRF52833 SoC.
Changes affect introducing:
- architecuture files (dtsi)
- configuration of nrfx drivers
- adaptation of inclusions based on chosen SoC
- configuration of NFCT_PINS_AS_GPIOS depends on HAS_HW_NRF_NFCT.
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
This patch introduces the support of the Low Power Timer
for the STM32WBxx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The SPI NOR driver requires that the size (in bits) be provided in the
devicetree node. Update the binding to make the property required,
and update all nodes based on the memory chip identified.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This patch introduces the support of the Low Power Timer
for the STM32L4xx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds supoprt for the Atmel SAME54 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the sam0 Cortex-M0+ and saml1x Cortex-M23 parts.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Introduce a standard watchdog alias 'watchdog0' that can be utilized
by sample/test code in the future. This helps remove the need for
CONFIG_WDT_0_NAME in dts_fixup.h files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
dts pinctrl definitions were pushed in tree without the code
available to deal with it. They have been kept waiting for the
code, but this is taking much more time than initially thought.
So in current zephyr tree, for all STM32 boards, we have pinmux.c
file which is used to configure pins and these files that are
basically no-op. This situation is creating a lot of confusion
especially to new comers, and create useless maintenance effort.
Remove these files for now.
When zephyr will ready to use them, this commit could be reverted.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit moves DMA parameters previously hard coded in the driver
to the dts.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There is no APB2 bus on stm32f0 series.
What could be found as APB2 in CMSIS files is actually
second group of APB (A.K.A APB1_2).
Fix nodes that are using this wrong reference accorss the series.
Fixes#20310
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move the selection of the IP clock source for the modules in the NXP
Kinetis KE1xF SoCs from being hardcoded in soc.c to being specified in
the device tree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
STM32L151XB-A SoC is almost similar to the STM32L151XB SoC except that
it has more RAM (32KiB). Hence add devicetree and Kconfig support.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Indtroduction of generic device tree bindings for keyboard scan devices.
In addition, device tree node entries and dt specific bindings where
also implemented for Microchip MEC1501
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
STM32L1 uses the same spi controller as STM32F1 so we can just set the
right addresses and enable them. We also need to add the fixup names and
to correctly include the header for ST LL HAL.
Signed-off-by: Karl Palsson <karlp@etactica.com>
1. Replace the non-existent CPU device binding ("Cortex-R") specified
by the CPU node with a proper one.
2. Relocate CPU node declaration to SoC dtsi:
The CPU node should be declared in the SoC dtsi because the core
type is SoC-dependent. In fact, this is exactly how it is done in
the Cortex-M port.
3. Remove core_intc (supposedly Cortex-R VIC):
Unlike the NVIC of Cortex-M, the VIC of Cortex-R is not a true
interrupt controller in the conventional sense and merely acts as
a CPU input port for aggregated interrupt request and vector index
signals. For this reason, there is no point in declaring it in the
device tree and specifying it as an interrupt parent. All SoCs
incorporating Cortex-R implement a separate true interrupt
controller (for instance, GIC for Zynq MPSoC and VIM for Hercules).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The patch adds initial support for STM32F030X4 SoC.
STM32F0 Cube package advises to use 'stm32f030x6' code
for both STM32F030x4 and STM32F030x6 SoC variants.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Add soc and dts files to support for most of the common peripherals
in the STM32G4 series. Add specific support for the STM32G431RB.
Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
Add #pwm-cells property in bindings for Nordic PWMs and add this
property with a suitable value assigned to all PWM nodes in dts
files for Nordic SoCs.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit introduces separate "compatible" strings for DTS nodes
representing different types of Nordic SPI peripherals. Previously
"nordic,nrf-spi" was used for both SPI and SPIM. SPIS was already
handled separately.
Quite a few files need to be touched by this commit but the changes can
be divided into groups of related or very similar ones, distinguishable
by the initial part of the path to the modified file:
* dts/bindings/spi/
new binding for "nordic,nrf-spim" is added and common fields for all
3 types of Nordic SPI peripherals are extracted to a shared file
* dts/arm/nordic/
"compatible" properties in spiX nodes are updated (when there is no
choice as only one type of SPI peripheral is available) or replaced
with a comment pointing out that the proper type of peripheral needs
to be picked at some upper layer
* drivers/spi/
spi_nrfx_spim driver is updated with the new form of macros generated
from dts
* boards/
all spiX nodes in dts files for boards equipped with an nRF chip are
updated with the proper "compatible" property, according to the type
of SPI peripheral that is currently selected for the board by the
corresponding Kconfig choice option (SPI_x_NRF_SPI*)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit introduces separate "compatible" strings for dts nodes
representing different types of Nordic TWI peripherals. Previously
"nordic,nrf-i2c" was used for both TWI and TWIM, and TWIS was not
supported.
Quite a few files need to be touched by this commit but the changes can
be divided into groups of related or very similar ones, distinguishable
by the initial part of the path to the modified file:
* dts/bindings/i2c/
new bindings for "nordic,nrf-twim" and "nordic,nrf-twis" are added
and the one for "nordic,nrf-i2s" is renamed to "nordic,nrf-twi",
common fields for all these bindings are extracted to a shared file
* dts/arm/nordic/
"compatible" properties in i2cX nodes are updated (when there is no
choice as only one type of TWI peripheral is available) or replaced
with a comment pointing out that the proper type of peripheral needs
to be picked at some upper layer
* drivers/i2c/
both flavors of i2c_nrfx drivers are updated with the new names of
macros generated from dts
* boards/
all i2cX nodes in dts files for boards equipped with an nRF chip are
updated with the proper "compatible" property, according to the type
of TWI peripheral that is currently selected for the board by the
corresponding Kconfig choice option (I2C_x_NRF_TWI*)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the device tree to assign the correct peripheral clock to each
UART/USART/LEUART. Previously, the clock identifier was determined
through the sequence number of the instantiated UART. This meant
configuring all UARTs when only one of the later UARTs was required.
Signed-off-by: Oane Kingma <o.kingma@interay.com>
This adds support for Kinestis K22
Co-authored-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Co-authored-by: Oliver Stäbler <oliver.staebler@bytesatwork.ch>
Co-authored-by: Tom Burdick <thomas.burdick@gmail.com>
Signed-off-by: Tom Burdick <thomas.burdick@gmail.com>
Add RTC timer driver for CC13X2/CC26X2, and use it instead of systick
as system clock. It is necessary to use this timer for power
management support, so that the system can exit from deep sleep upon
expiry of timeouts.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
4 are found: 2 with a counter of 16bits and 2 with a counter of 32 bits.
However, first 32bits instance will not be exposed as it will be used by
rtos timer driver directly to implement k_busy_wait()
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The driver for STM32's independent watchdog already exists and is
compatible with the stm32wb SoC. Enable the independent watchdog
for the stm32wb series for use with this driver.
Signed-off-by: Robert Weber <robertweber95@gmail.com>
The KE1xF SoC family SIM unit differs from the other Kinetis family
SoCs. Add a unique compatiable and binding for it.
Fixes#18160
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For quite a few peripherals that are currently supported by nrfx HALs
or drivers there are no definitions of corresponding CMSIS-Core
peripheral accessing symbols that would provide their base addresses
in the proper domain (secure or non-secure), accordingly to the build
target. This commits adds devicetree nodes for these peripherals so
that their base addresses can be used in definitions of the accessing
symbols mentioned above.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Pull out the LPO fixed-clock that is part of the PMC hardware block as
its own child node of the PMC block. This is because the PMC could have
its own driver associated with it that is seperate from the LPO clk.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Update the ADC bindings to include #io-channel-cells and update the
related dts files to set #io-channel-cells.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
'interrupt-parent' should contain just the phandle of the node
interrupts are sent to.
This node (gic: interrupt-controller@f9010000) doesn't generate any
interrupts, so the 'interrupt-parent' value is never used (this is why
it wasn't caught). It'll give an error later with 'interrupt-parent'
declared as 'type: phandle' in bindings though.
Don't know what was intended. Just remove the 0.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
SPI3 clock info were missing and following macros were
not generated:
- DT_ST_STM32_SPI_FIFO_40003C00_CLOCK_BITS
- DT_ST_STM32_SPI_FIFO_40003C00_CLOCK_BUS
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based
platform for Cortex-R based testing. This SoC only supports an
interrupt controller and serial port for limited testing.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Remove unused "system-clock-frequency" property, we don't have this
defined in various bindings and thus aren't using it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use clock specified in the device tree for obtaining the source clock
frequency for the pwm_mcux_ftm driver instead of relying on having an
NXP Kinetis MCG clock available in all SoCs supporting FlexTimer (FTM)
modules.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
NRF_UICR needs to be defined for nRF9160 SoC in
nrfx_config_nrf9160.h, because it is not defined
in nrfx/hal/mdk/nrf9160.h (as it is a Secure-only
peripheral).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
With the new DT checks the dts bindings for "nxp,flexpwm" and
"nxp,imx-pwm" had old conventions that we now treat as build errors.
Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
i.MX RT10XX processors have four eFlexPWM modules, each containing
four 2-channels PWM submodules.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
The true mmio-sram nodes should not have had a 'device_type' property.
Remove it from the cases that we clearly know are SRAM.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
These are not declared in dts/bindings/arm/nxp,kinetis-sim.yaml and do
not generate any output.
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
A minor spelling fix in an inline comment in
both nRF9160 Secure and Non-Secure .dtsi headers.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
These are not declared in any binding and do not generate any output.
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Fix the following dtc warning:
mimxrt1064_evk.dts.pre.tmp:78.31-85.5: Warning (spi_bus_bridge):
/soc/flexspi1@402a4000: node name for SPI buses should be 'spi'
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Several aliases were added to nrf9160[ns].dtsi files solely for
the purpose of getting base addresses of certain hardware modules
via DT_ macros generated for these aliases.
Since for one-instance modules the same can be now achieved with
standard DT_INST_0_* macros, there is no need to keep these aliases.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
pinmux: Add the relevant definition of the spi3 pin
dts: Fix a bug, spi3 does not have a label
soc: Supplement spi3 related definition
Signed-off-by: Findlay Feng <i@fengch.me>
stm32f429.dtsi wrongly introduced i2s nodes 4, 5 and 6.
Remove them as actually only i2s nodes 2 and 3 are supported on
these socs.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This was always intended to be a bytestring rather than an array, but
full support was missing. Since that has been addressed switch it to
the preferred format.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The property is required on all SPI clients, but was missing from
several devicetree nodes. Set it, using the capitalized version of the
node alias when present, with "jedec,spi-nor#0" as the fallback.
Closes#17662
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Have the SoC dtsi files for microchip mark the devices (uart & i2c) as
disabled by default and let the board dts files enable which one's they
need/use (which is what's happening already).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
spi-max-frequency is marked as required in
dts/bindings/mtd/jedec,spi-nor.yaml.
I took the value from the datasheets (133 MHz for all), and guessed that
a dummy entry is fine for QEMU.
Fixes some errors in
https://github.com/zephyrproject-rtos/zephyr/issues/17532.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
There doesn't seem to be any use of the virtualcom device in the code,
so lets remove it from the dts as it describes itself as a usb device
controller which it is not.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds a fixed clock node (representing clock driving
system bus). The added node is then referenced by peripherals requiring
information about driving clock frequency.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit adds 'clock-frequency' property to the cpu nodes.
The clock frequency specified in the added property is used
during platform configuration. Examples:
- The SWO logger uses clock frequency to configure SWO output.
- Plenty of platforms need CPU clock specified for their HAL.
- Most of devices with USB needs information about CPU clock
in order to configure USB clock source.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This patch populates "clocks" property in stm32 usb nodes
for clock related usb configuration code of each dtsi files
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The spi-nor flash nodes require a jedec-id property as per the binding.
We add the jedec-id's as best we can determine based on the data sheets
for the various flash modules on these boards.
However these id's should be validated by actually reading the value to
ensure they are correct.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix USB phy node for stm32l432 and stm32l452, which contain
a USB controller and not a OTG FS controller.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
1) dts/bindings/mmc/mmc.yaml: specifies common mmc.
2) dts/bindings/mmc/nxp,imx-usdhc.yaml: specifies
nxp usdhc module which inherits mmc.
3) dts/arm/nxp/nxp_rt.dtsi: usdhc support on RT chip.
4) boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts:
usdhc slot support on mimxrt1050_evk board.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
A number of minor issues with the 'fixed-clock' support:
* Fix the #clock-cells to be 0
* Fix nxp_ke1xf.dtsi to set #clock-cells 0 and the clock reference to
only be a phandle.
* Fix the generation script to only generate what it should for a
'fixed-clock'
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add clock support for STM32G0X SoC series.
Signed-off-by: Philippe Retornaz <philippe@shapescale.com
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch adds support for the STM32G071xx
from STMicroelectronics.
Signed-off-by: Philippe Retornaz <philippe@shapescale.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Allow individual specification of the time quanta used for the CAN bus
propagation segment and phase segment 1.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added support for the STM32L496XE series with 512KB internal flash and
256KB SRAM of contiguous addresses.
Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
The DT spec. only has "okay" and not "ok". The Linux kernel has around
12k "okay"s and 300 "ok"s.
The scripts/dts scripts only check for "disabled", so should be safe re.
those at least.
The replacement was done with
git ls-files | xargs sed -i 's/status\s*=\s*"ok"/status = "okay"/'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit adds counter driver based on RTCC module for SiLabs Gecko
SoCs.
Tested with SLWSTK6061A / BRD4250B wireless starter kit.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
stm32wb55rg is a dual core SoC (M4/M0) with a radio/protocol stack
running on M0 core. M0 FW starts at flash address 0x80CB000.
So flash size available to zephyr is 812K instead of 1M.
Configure package size to reflect this (flash size is now 812K)
and update MPU setting to exclude M0 FW. From MPU point of view,
we set flash size to 512K since we should chose a size being a power
of 2.
If we consider there will be 2 images partitions in a FOTA scheme,
512 K is beyond image-0 and hence is sufficient to cover application
image.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
sram2a and sram2b where defined in the prospect of defining
HCI shared memory sections from device tree.
Remove them, since this is not the case anymore.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Christian Taedcke