DMA controller is enabled and tested for cortex M7 core. The M7 core was
tested on the loop and channel link transfer tests.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds support for editing the voltage levels on the buck
regulators on the PCA9420 PMIC
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds a generic i2c regulator driver, and enables the NXP
PCA9420 PMIC IC using this driver. The regulator driver also exposes an
additional API in include/drivers/regulator/consumer.h, which allows
drivers to implement support for adjusting voltage levels and current
limits, if their device supports it.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
the RT685 contains an additional flexcomm peripheral, that supports
only I2C. This commit adds this peripheral to the device tree,
and enables pins and clocks for flexcomm15.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Catch up on the CAN driver API argument naming changes:
- Unify naming of callback function pointers as "callback".
- Unify naming of user-specified callback function arguments as
"user_data".
- Instances and pointers to struct zcan_frame are named "frame",
not "msg", to avoid confusion with the CAN message queue support.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit adds Xen consoleio serial driver. It is needed to receive
kernel messages from Zephyr in case it runs as Xen privileged domain
(Dom0). There is no console ring buffer for such domain, so regular
uart_hvc_xen driver can not be used (privileged domain input/output
are possible only through consoleio interface).
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
This commit adds support of interrupt-driven API for UART-like Xen PV
console driver. It is implemented via Xen event channels. It allows to
send and receive data by chunks (not single symbols) and without
polling.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
This commit adds support of Xen Enlighten page and initial support for
Xen event channels. It is needed for future Xen PV drivers
implementation.
Now enlighten page is mapped to the prepared memory area on
PRE_KERNEL_1 stage. In case of success event channel logic gets
inited and can be used ASAP after Zephyr start. Current implementation
allows to use only pre-defined event channels (PV console/XenBus) and
works only in single CPU mode (without VCPUOP_register_vcpu_info).
Event channel allocation will be implemented in future versions.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
In #40140, all on-chip gpios where made to use `CONFIG_GPIO_INIT_PRIORITY`.
The lmp90xxx and sx1509b are off-chip gpios. This commit reverts those
changes for these two devices.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
Adds a driver using the SNVS high power and optionally low power
RTC instances. A device specific function `mcux_snvs_rtc_set` is
provided to update the current counter value.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Update the SPI context during all transceive functions. This fixes a
deadlock where SPI transactions failed to give back the semaphore.
Verified on NPCX9 based Chromebook.
Signed-off-by: Keith Short <keithshort@google.com>
The internal functions of this driver needed either `device *`
or `st7789v_data *` as argument. Standardize to
using `device *`.
Signed-off-by: Casper Meijn <casper@meijn.net>
RT11xx USDHC lacks some watermarking features that RT10xx SOCs include.
Place #ifdef guards around these features.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This adds an spi master mode driver via bitbanged gpio. Only syncronous
transfers are implemented. Clock signal timing is accomplished via busy
waits, the gpios are manipulated via the standard gpio interface; these
two factors limit the frequency at which it can operate - but here
a simple and generic implementation was chosen over performance.
The driver supports the various clock polarity and phase
configurations, and can also work with word sizes which are non
multiples of 8bits, currently up to 16 bits.
A sample program is also added demonstrating basic use of the driver
with 9bit data words.
Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
Rename the PM_STATE_DT_ITEMS_LIST macro to PM_STATE_LIST_FROM_DT_CPU to
make its purpose more clear. Similar naming scheme is found e.g. in the
GPIO API.
Associated internal macros and docstrings have been adjusted, too.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
A couple of drivers violated MISRA 5.7 rule (Tag name should be unique),
triggering CI compliance errors.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
A Cortex-M specific function (sys_clock_isr()) was defined as a weak
function, so in practice it was always available when system clock was
enabled, even if no Cortex-M systick was available. This patch
introduces an auxiliary Kconfig option that, when selected, the ISR
function gets installed. External SysTick drivers can also make use of
this function, thus achieving the same functionality offered today but
in a cleaner way.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
- Remove the weak symbol definition
- Notify about the capability of disabling via a selected Kconfig option
(CONFIG_SYSTEM_TIMER_HAS_DISABLE_SUPPORT)
- Provide a dummy inline function when the functionality is not
available
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Split Kconfig into individual files for each driver. This improves
overall readability of the Kconfig options.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The weak symbol sys_clock_driver_init has been removed, therefore moving
the init responsability to the drivers themselves. As a result, the init
function has now been made static on all drivers and moved to the
bottom, following the convention used in other areas.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Adds the ability for I2C drivers to report synchronous transfer stats
using a I2C specific macro to define the device instance.
The macro creates a container for device_state which allows for per
instance device class common data structure to be used in the device
class api (ex: i2c.h). This is used to maintain per driver instance
stats for all i2c drivers. This is a reusable idea across other device
classes as desired.
Using Kconfig device class stats may be turned on/off individually
this way as well, in this case I2C_STATS.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
MCUX PWM driver used hardcoded clock source. update driver to use clock
bindings to determine PWM peripheral clock frequency.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds optional device tree properties to insert delays between spi chip
select assert/deassert and the clock edges, and also between spi
frames and transfers to the mcux flexcomm spi driver. If the properties
are not set, no additional delay is inserted.
Verified expected behavior on mimxrt685_evk and check with a scope
that the pre- and post-delay could be changed from the device tree
properties.
Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
The UART1 is not actually accessible on the HiFive1 since the
QFN48 package for the FE310, used by this board, does not expose the
required pads. However, it is still possible to use the UART1 on HiFive1
emulators (e.g. using UART0 for debugging and UART1 for SLIP).
Unfortunately, the UART0 and UART1 currently have different default
configurations when it comes to the configured transmission watermark
(txcnt). With a txcnt of zero (the default for UART1) the UART is not
actually usable (see #18118). Contrary to UART0 (see #23699), the UART1
does therefore not work by default on Zephyr which took me some time to
figure out.
This commit aligns the default UART1 configuration with the UART0,
thereby making it work by default.
Signed-off-by: Sören Tempel <tempel@uni-bremen.de>
Instead of busy wait until completed transaction, the constraint set
is used before enabling tx interrupt to not allow system to enter
suspend when tx is transmitting.
Application defined policy should use the pm_constraint_get function
to check if given state is enabled and could be used.
TEST=Test on hayato board(soc:it8xxx2), the logs print normally before
system enters suspend.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
After the commit "dts: ksz8974: change port number to start at zero."
(SHA1: aa6217697e)
the lan ports are numbered starting from zero (not as previously from
one), so code assigning tags shall take this into account.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After the "dts: ksz8974: add support for ksz8863"
(SHA1: b0e4886dfa) commit the port numbering
for KSZ8794 was wrong.
This IC has 3 ETH ports (with linear offset), with port 4 being the
"master" with non linear offset (i.e. 0x50 instead of linear 0x40).
Such situation can be explained with similarity of this IC to ksz8795,
which has 4 LAN ports, and then the 0x40 offset is used.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The name of macro to enable tail tagging support in DSA KSZ driver is
CONFIG_DSA_KSZ_TAIL_TAGGING, not DSA_KSZ_TAIL_TAGGING.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The check for CPU port on the KSZ8794 when the switch is initialized,
is not required as the last port number is always smaller than the CPU
port.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The device PM callback needs to be used only to suspend/resume devices.
If the system cannot be suspended because UART is in a particular
state, the pm_constraint_set/release API should be used. For NPCX UART,
the chip can't enter low power idle state until UART completes the data
transmission.
This commit changes NPCX UART to use pm_constraint_set/release & fixes
UART lost data from low power idle.
Fix#40621
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
- added messages check and fix before transfer
- fixed START and STOP signal generation conditions
- fixed semaphore release for empty messages
Signed-off-by: Konrad Sikorski <znfgnu@gmail.com>
Fixes: #40538
The TEMP_NRF5 setting requires MULTITHREADING, therefore add this
dependency to Kconfig.
The TEMP_NRF5 supports an alternative driver implementation using the
TEMP_NRF5_FORCE_ALT setting.
Because it cannot be known whether an alternative implementation has
the same dependency, then the MULTITHREADING is OR'ed with
TEMP_NRF5_FORCE_ALT, as to allow enabling of TEMP_NRF5 if an alternative
driver is provided.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit adds support for IMX6SX PWM.
The PWM module is the same module present on the IMX7D and so dts
bindings has been renamed following the one present on linux.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Adds DMA support to NXP's LPSPI driver. This can be enabled by selecting
the KConfig symbol CONFIG_SPI_MCUX_LPSPI_DMA, and requires the LPSPI
instances enabled in the devicetree to have valid DMA instances
assigned.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Without this change, when DTS SPI device node has node ID = <0>, the
value of 0 is assigned during SPI configuration and written to
whichPcs member in master_config structure.
This value wrongly overrides the default value read from NXP's DSPI
HAL (kDSPI_Pcs0 = 1U << 0).
Such situation occurs on ip_k66f board, where the DSA device -
controlled via SPI has the node ID equal to 0 (i.e. reg = <0>).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit is enabling the Debug support clock
like the stm32L0 or F0, the APB peripheral clock enable register 1
has a bit to clock DBGMCU before use.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is controlling the WWDG during the Stop mode in debug.
WWDG1 is frozen while the core is in Debug mode, setting the bit
of the DBGMCU APB1 peripheral freeze register (DBGMCU_APB1FZ2)
for the stm32MP1 soc devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is controlling the WWDG during the Stop mode in debug.
WWDG1 is frozen while the core is in Debug mode, setting the bit
of the DBGMCU APB3 peripheral freeze register (DBGMCU_APB3FZ1)
for the stm32H7 soc devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove check if frequency is equal to zero. A value of `ODR = 0` is
explicitly allowed by manufacturer / datasheet.
This has prevented applications from using the lis2dh power-down-mode,
which is set via `ODR = 0`.
For reference see "Table 28. Data rate configuration" in datasheet p.33.
Fixes#35486.
Signed-off-by: Markus Brüx <markus.bruex@grandcentrix.net>
Daniel DeGrasse