Some modems, under some conditions, have a tendency to get stuck without
a connection due to cached state. We have observed this on some Simcom
LTE modems after large cellular outages. The modems are unable to escape
their cached state for some reason unless they're factory reset (or a
cache clearence is forced in some other way).
This commit allows for the modem to be factory reset at each boot. This
minimizes dependencies on external state by ensuring each power-up is as
similar as possible.
Signed-off-by: Benjamin Lindqvist <benjamin.lindqvist@endian.se>
Fix#32918 [Coverity CID :219528] "Arguments in wrong order
in tests/drivers/pwm/pwm_loopback/src/main.c"
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
Currently RAM region specified in the DT for board mps2-an512 to store
data (not to run code) is set to start at 0x3000_0000 and a 16M
contiguous space is assumed. However, at that address there is no such
contiguous space of 16M, rather only a 128K area is available. As a
consequence large applications linked with Zephyr might end up using
memory regions that are not valid, specially at runtime when the stack
grows, causing a BusFault.
Application Note 512 only specifies a 16M contiguous space available
starting at 0x8000_0000 (please see 'Table 3-4: SSRAM2 and SSRAM3
address mapping' and 'Table 3-6: External PSRAM mapping to Code Memory',
on pages 3-7 and 3-8, respectively), which resides in the PSRAM
(external RAM).
The AN521 also specifies a 4M contiguous space available starting at
0x3800_0000 which can be used as RAM for data storage and which is not
currently described in the DT.
The current DT also defines a 224M flash region (to run code) which
doesn't effectively exist, because most of it is reserved (~148M).
That commit fixes the incorrect definition of region 0x3000_0000 (16M)
and hence defines a new region called 'sram2_3' that maps to region
0x3800_0000 (4M) which is used as RAM to store data, and fixes the flash
region defining a new region 'sram1' (4M) from where code is executed
(starting at 0x1000_0000). The board has no real flash memory, rather an
auxilary HW populates the appropriate memory regions from images found
in a MicroSD card.
That commit also defines the missing PSRAM (16M) region ('psram') which
can be used by large programs as a general purpose RAM.
Finally, it also fixes the DT for the non-secure memory regions to
reflect the fixes described above for the secure memory regions.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
The mps2_an521_nonsecure exists for TFM and is also utilized as a config
for multicore samples. We can enable just the TFM tests with only_tags
and get a bit of additional coverage in QEMU for the TFM integration.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
CORTEX_M_SYSTICK is enabled by default on all STM32 based targets,
in common soc Kconfig files.
Forcing its definition in board files is redundant and prevents
to disable it when activating LPTIM as ticker.
Remove these definitions
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of listing Python dependencies in the docs, refer to the
requirements file. This way docs are never out of sync.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
It is easier to follow the user guide if each platform has its own tab
for requirements.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Current DW I2C driver uses 32 bit access for some registers and
16 bit access for others. So if DW I2C IP is connected via bus
which doesn't support 16 bit access we will get bus error.
Fix that by switching to 32 bit access only instead of 16
and 32 bit mix.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Use an "initiated" flag in the lll_conn struct to guard the processing
of PDUs related to connection initiation (CONNECT_IND,
AUX_CONNECT_RSP). This avoids races between ULL and LLL when creating
a connection.
Signed-off-by: Wolfgang Puffitsch <wopu@demant.com>
As this header declares a function that uses a cube defined structure
as argument, it should include the matching header.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Test to ensure that a reset with a waiting thread properly aborts the
wait, and the semaphore remains functional after.
Signed-off-by: James Harris <james.harris@intel.com>
Previously, a k_sem_reset with any outstanding waiting threads would
result in the semaphore in an inconsistent state, with more threads
waiting in the wait_q than the count would indicate.
Explicitly -EAGAIN any waiting threads upon k_sem_reset, to
ensure safety here.
Signed-off-by: James Harris <james.harris@intel.com>
check_interface resets the counter semaphore, but
net_config_init_by_iface first calls check_interface, then inits
the semaphore.
Initialize the semaphore up front to allow the k_sem_reset call
to work properly.
Signed-off-by: James Harris <james.harris@intel.com>
Debugging long-tail semaphore test failures currently is rather
annoying, both because many semaphore test failures do not print
their failing values, and because some semaphore tests do not
check return codes, leading to test failures well after the actual
failure.
Redo the semaphore tests to at least give consistent failure
messages including the actual return code and consistently check
return codes of k_sem_* APIs.
Also driveby-fix several places that used an insufficiently-
sized type to store k_uptime.
Signed-off-by: James Harris <james.harris@intel.com>
With _kernel_offset_to_nested, we only able to access the nested counter
of the first cpu. Since we are going to support SMP, we need accessing
nested from per cpu.
To get the current cpu, introduce z_arm64_curr_cpu for asm usage,
because arch_curr_cpu could not be compiled in asm code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add SMP support.
Note: there is still limitation that we rely on NUM CPUs.
And all cpus must be from 0,1,2 and ....
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This only fix several test cases failed while running code coverage
report inmps2_an385 platform. Enlarge the stack size for which failed
due to MPU fault of stack overflow.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
If Zephyr is running on a coprocessor we might lack I/O
such as uart or usb to output tracing datas but we might
have gigabytes of RAM available.
This patch allows to output trace datas to a ram buffer, which then
may be retrieved using gdb.
e.g:
(gdb) dump binary memory channel0_0 <ram_tracing_start> \
<ram_tracing_end>
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
In C, `void foo(void);` and `void foo();` mean subtly different things.
The former means "foo takes zero arguments"; the latter means
"foo takes an unspecified number of arguments". This can result in
calling convention mismatches in exceptional cases.
Change to emitting `(void)` instead of `()` for a syscall with
zero arguments.
Signed-off-by: James Harris <james.harris@intel.com>
There was an error in the ordering of the parameters in the
DEVICE_DT_DEFINE for the native POSIX counter. This made a project
using a counter built for native posix not being able to compile.
This commit switches places for ctr_init and device_pm_control_nop.
Signed-off-by: Tofik Sonono <tofik@sonono.me>
add CAN_1 and CAN_2 hw modules support
Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
Co-authored-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Currently there is no way to distinguish between a caller
explicitly asking for a semaphore with a limit that
happens to be `UINT_MAX` and a semaphore that just
has a limit "as large as possible".
Add `K_SEM_MAX_LIMIT`, currently defined to `UINT_MAX`, and akin
to `K_FOREVER` versus just passing some very large wait time.
In addition, the `k_sem_*` APIs were type-confused, where
the internal data structure was `uint32_t`, but the APIs took
and returned `unsigned int`. This changes the underlying data
structure to also use `unsigned int`, as changing the APIs
would be a (potentially) breaking change.
These changes are backwards-compatible, but it is strongly suggested
to take a quick scan for `k_sem_init` and `K_SEM_DEFINE` calls with
`UINT_MAX` (or `UINT32_MAX`) and replace them with `K_SEM_MAX_LIMIT`
where appropriate.
Signed-off-by: James Harris <james.harris@intel.com>
Remove stale references to v2m_musica in the ipc samples as the board
support for v2m_musca has been removed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Maximum GIC SPI is 228, so maximum INTID is 228 + 32 = 260.
So, _sw_isr_table needs to support 260 entries
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Update register addresses and NVIC/GIC interrupt numbers
according to the latest viper RTL version.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
If a shell command is compiled out using SHELL_COND_CMD(),
a line for this command will still be printed but will
be blank. Change it so compiled out commands are not
listed as blank lines.
Signed-off-by: Pete Skeggs <peter.skeggs@nordicsemi.no>
Added CLOCK_CONTROL_NRF_FORCE_ALT dependency to some options which
are not valid when clock is controlled by out-of-tree driver.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Modified CLOCK_CONTROL_NRF_ACCURACY to represent integer value of
LF clock accuracy.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The test case suggests that "For most arch which support
userspace, derefencing NULL pointer will be caught by
exception.". This is certainly not true for Cortex-M, where
read access to address 0x0 is generally allowed. The reason
the test had been passing was either 1) because in many
Cortex-M platforms, including QEMU, address 0x0 is unmapped,
or 2) GCC is generating an undefining instruction. However,
now that we have activated the null pointer derefrencing
detection, we may end up with two exceptions and the test
would fail.
Change illegal access to something outside the mapped memory
area, e.g. 0xFFFFFFFF.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In the arch/arm test suite there are tests running with
CONFIG_NO_OPTIMIZATIONS enabled, and may require a
larger idle thread stack size.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Benjamin Lindqvist