In order to increase code coverage, we force building a Secure
Firmware image by default (i.e. with option
CONFIG_TRUSTED_EXECUTION_SECURE set), when building for
mps2_an521 board. CONFIG_TRUSTED_EXECUTION_SECURE enables
compiling-in all TrustZone-related code in the tree, that is,
all ARM-specific code inside #ifdef CONFIG_ARM_SECURE_FIRMWARE.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board.
Memory is tight so a few tests had to be disabled due to the extra
memory usage compared to qemu_riscv32.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add support for driving the on-board LEDs present on the NXP TWR-KE18F
development board using FlexTimer (FTM) PWM modulation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The number of MPU regions appears to be 16 instead of 8,
so we fix that in the board .dts files.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
So far zephyr.elf file was hardcoded in cmake files. Remove it from
there and use cfg.elf_file from python, which can be overwritten by
specifying --elf-file command line option.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Same deal as in commit a84ded74ea ("dts: Replace status = "ok" with
status = "okay""), for newly introduced stuff.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Route these to the equivalent pins for RXD1 and TXD1 on the Arduino
Mega.
Note that uart0 is routed to the debug probe IC on the nRF9160
DK, and uart1 is routed to where the RXD0 and TXD0 Arduino pins are on
the DK. This makes RXD1/TXD1 a logical place to put these UART pins,
since the header layout for the DK board matches the Arduino mega.
This is also necessary to keep some downstream code compiling which
needs to enable the UART2 but doesn't have a good place to put these
pins, since the new DTS parser is enforcing that all required
properties (like tx-pin and rx-pin in this case) are set for nodes
with status = "okay".
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
- update doc for different core configuration.
- fix some bugs in dts related files.
- add dts config and defconfig for different core configuration.
- end files with a newline in boards/arc/emsdp/board.dtsi
- remove unused head in boards/arc/emsdp/doc/index.rst
- ARC_MPU_VER in different core is fixed. so remove some useless code
for ARC_MPU_VER judgements in Kconfig.defconfig.* files for emsdp
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Enable Mailbox support on 96Boards Avenger96 board. This will help
communicating to CortexA7 core.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Add onboard LEDs on 96Boards Avenger96 board. There are 4 user LEDs
on this board but only 3 are enabled. This is due to the fact that
LED0 is connected to unavailable PortZ. Hence, LED0 is ignored and
remaining LEDs are enabled starting from index 0.
Once PortZ is added, this will be fixed.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
After witnessing some strange errors with memory not being
what it should be, lifiting everything above 1MB has solved
it. The Zephyr binary was being loaded into memory containing
reserved regions, resulting in data corruption.
We still simulate XIP for testing purposes by setting up the
memory map as follows:
0x000000 - 0x0FFFFF : Non-present
0x100000 - 0x4FFFFF : "Flash" ROM region
0x500000 - 0x8FFFFF : "SRAM" RAM region
For a total of 9 megabytes of physical RAM used.
Fixes problems observed in some large tests when code coverage
is enabled (which increases the amount of RAM used even more).
Fixes: #17782
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Removes very complex boot-time generation of page tables
with a much simpler runtime generation of them at bootup.
For those x86 boards that enable the MMU in the defconfig,
set the number of page pool pages appropriately.
The MMU_RUNTIME_* flags have been removed. They were an
artifact of the old page table generation and did not
correspond to any hardware state.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For OpenVega board, in the case of the Zero Riscy core,
the flash partition used for the code and data is the
M0 ARM core's 256KB flash region. This is closest to
the RISC core.
The m0_flash node defines where the interrupt vector
is located for the Zero Riscy core, and one needs to
restrict the application so its interrupt vector is
placed accordingly.
Fixes: 34b0516466 ("boards: riscv32: rv32m1_vega:
enable MCUboot for ri5cy core")
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
It is expressed that the BOARD depends on whether NONSECURE is enabled
or not. But it is the other way around. Depending on the selected
board, it may or may not be possible to enable/disable NONSECURE.
The dependency is going in the wrong direction, this reversed edge is
observed to be able to create a cycle in the dependency graph.
Fix the dependency by removing it.
It is left as future work to enforce that enabling/disabling NONSECURE
is done in a way that is compatible with selecting
BOARD_NRF9160_PCA10090 vs BOARD_NRF9160_PCA10090NS.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
The "{d,i}ccm" nodes should not have had a 'device_type' property.
Remove it from the cases that we clearly know are {d,i}ccm.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The true mmio-sram nodes should not have had a 'device_type' property.
Remove it from the cases that we clearly know are SRAM.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add SPI support for stm32mp157c_dk2 board. If SPI is selected, SPI4
(Arduino connector compatible SPI) and SPI5 (on front 2x20 GPIO
expander) will be enable by default on stm32mp157c_dk2 board.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
(This could not be triggered in the nrf52_bsim yet,
so just so it is fixed for the future)
Properly handle converting back and forth from absolute to HW
time when either of those is set to TIME_NEVER
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
System clock for m4 core was set to same clock as m7 core.
This is wrong as m4 its value is actually based on clock frequency
value after D1CPRE (sys_d1cpre_ck) divided per HPRE value, 200MHz in
current case.
This also matches the max clock speed for the m4 core (200MHz)
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
cores
In order to prevent potential misconfiguration set the clock setting,
which impacts both cores, under board.defconfig file which is used
by both core.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32 clock control subsystem allows to configure a different
frequency value for core clock (SYSCLK) and AHB clock (HCLK).
Though, it is HCLK which is used to feed Cortex Systick timer
which is used in zephyr as reference system clock.
If HCLK frequency is configured to a different value from SYSCLK
frequency, whole system is exposed to desynchro between zephyr clock
subsytem and STM32 HW configuration.
To prevent this, and until zephyr clock subsystem is changed to be
aware of this potential configuration, enforce AHB prescaler value
to 1 (which is current default value in use for all STM32 based
boards).
On STM32H7, enforce D1CPRE which fills the same role as ABH precaler.
On STM32MP1, the equivalent setting is done on A7 core, so it is
not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC
is set with the 'mlhclk_ck' clock frequency value. Update
matching boards documentation.
Fixes#17188
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Adapted from similar code in the x86_64 port.
Useful when debugging boot problems on actual x86
hardware if a JTAG isn't handy or feasible.
Turn this on for qemu_x86.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Write all the desired values in the debug control flag.
Initally we were oring it, but this variable does not have
the expected initial values as it also depends on fuse
programming settings, therefore we dont have console.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Allow the user to use software slave select instead of the
hardware pin, in order to free the related GPIO and avoid
unwanted SS triggering on the hardware pin. The default SS
is still the hardware pin.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
ARC nSIM simulates pretty much any modern ARC core,
moreover it emulates a lot of different core features so
it is possible to play with them even wo real hardware.
Thus we add yet another ARC core family to be used on simulated
nSIM board.
For now it's just a basic configuration with ARC UART for
smoke-testing of Zephyr on ARC HS CPUs.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
The ARC HS is a family of high performance CPUs from Synopsys
capable of running wide range of applications from heavy DPS
calculation to full-scale OS.
Still as with other ARC cores ARC HS might be tailored to
a particular application.
As opposed to EM cores ARC HS cores always have support of unaligned
data access and by default GCC generates such a data layout with
so we have to always enable unaligned data access in runtime otherwise
on attempt to access such data we'd see "Unaligned memory exception".
Note we had to explicitly mention CONFIG_CPU_ARCEM=y in
all current defconfigs as CPU_ARC{EM|HS} are now parts of a
choice so we cannot simply select ether option in board's Kconfig.
And while at it change "-mmpy-option" of ARC EM to "wlh1"
which is the same as previously used "6" but matches
Programmer's Reference Manual (PRM) and is more human-friendly.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This will give us a possibility to check unaligned read/write support
in simulation.
Note nSIM with S(ecure)EM (with secure option) doesn't support that
mode in HW.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Musca B1 has 2 x 2MB embedded flash memories (eFlash). The flash
memories are connected to the AHB Master Expansion “Code Interface”.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
This property is only declared in bindings/spi/nordic,nrf-spis.yaml ('s'
for 'slave'), not in bindings/spi/nordic,nrf-spi.yaml.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Add the link between the i2c and the arduino connector,
here i2c5.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@linaro.org>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@linaro.org>
I2C5 are used by arduino connector.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@linaro.org>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@linaro.org>
We generated a define for each instance to convey its existance of the
form:
#define DT_<COMPAT>_<INSTANCE> 1
However we renamed all other instance defines to be of the form
DT_INST_<INSTANCE>_<FOO>. To make things consistent we now generate a
define of the form:
#define DT_INST_<INSTANCE>_<COMPAT> 1
We also now deprecate the DT_<COMPAT>_<INSTANCE> form and fixup all uses
to use the new form.
Fixes: #17650
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
As we now have PPP support, use more generic "serial-net" string instead
of "slip" when setting what kind of networking the board supports.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Expose eSPI block with interrupts enabled for channel 0 & 1
eSPI handshake has been tested using espi driver sample app
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This was always intended to be a bytestring rather than an array, but
full support was missing. Since that has been addressed switch it to
the preferred format.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Particle released documentation with a pre-release flash chip. Correct
the name to the actual as-sold device, and add the corresponding size
property as well as the has-be32k property. Also add an alias so we
can set partitions externally.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The JEDEC API defines the hardware page, sector, and block sizes.
Deprecate the Kconfig settings, remove the `erase-size-block` property,
and add `has-be32k` to indicate that 32K-byte erase is supported.
Rework the driver to use the constants instead of configured values.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The uart node in the native_posix dts has a reg property, but there are
no registers associated with the uart. So remove the property and
remove the unit address associated with the reg (now that its removed).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Clarify a little bit how to fetch and compile Babblesim.
So users will not need to have repo installed,
and to guide them to add the variables to their shell init
script
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
The property is required on all SPI clients, but was missing from
several devicetree nodes. Set it, using the capitalized version of the
node alias when present, with "jedec,spi-nor#0" as the fallback.
Closes#17662
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The binding for arm,cmsdk-timer requires a label so add it into the dts
since its missing on v2m_musca_b1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The bindings for arm,cmsdk-{d}timer requires a label so add it into the
dts since its missing on mps2_an521.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
spi-max-frequency is marked as required in
dts/bindings/mtd/jedec,spi-nor.yaml.
I took the value from the datasheets (133 MHz for all), and guessed that
a dummy entry is fine for QEMU.
Fixes some errors in
https://github.com/zephyrproject-rtos/zephyr/issues/17532.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Activate the DTCM for STM32F7 board that have Ethernet.
This is needed because the Ethernet driver puts the DMA buffer
to this section.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
Qemu_x86 didn't reflect emulated program memory size.
It was because chosen zephyr,flash was assigned to flash_simulator
which was helping to generate DT_FLASH properties for sim_flash node.
This change revert choice of flash0 which solve problem with
program memory size. Flash simulator have to use
DT_SOC_NV_FLASH_xxx labels for fetch its property since that.
fixes#15832
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
The desired memory map is to have the 0 - 4K page non-present
to catch NULL pointer dereferences,
from 4K - 4MB for the program text (RO, Execute),
ROM (RO, No Execute), and 4MB-8MB for system RAM.
This patch cut text size by 4 KB which allow to meet above
requirements.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
This commit adds a fixed clock node (representing clock driving
system bus). The added node is then referenced by peripherals requiring
information about driving clock frequency.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit adds 'clock-frequency' property to the cpu nodes.
The clock frequency specified in the added property is used
during platform configuration. Examples:
- The SWO logger uses clock frequency to configure SWO output.
- Plenty of platforms need CPU clock specified for their HAL.
- Most of devices with USB needs information about CPU clock
in order to configure USB clock source.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
When TRUSTED_EXECUTION_NONSECUCRE is selected, we always
define the default board (mps2_an521). We do not need to
OR with TRUSTED_EXECUTION_SECURE, in this Kconfig
conditional.
In addition to that, we make the BOARD_MPS2_AN521 board
to strictly depend on the corresponding SOC, not on the
SOC series.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Signify that the MPS2 AN521 is selected as a QEMU
target. Indicate, also, that this board has support
for COVERAGE.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
CONFIG_ARCH_HAS_USERSPACE is automatically set for
Cortex-M targets with CONFIG_ARM_MPU being set. So
we can remove this from the default setup since it
is redundant.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Because the only difference between native_posix and native_posix_64
should be 32-bit vs 64-bit compilation, the NATIVE_POSIX menu option
is turned into NATIVE_POSIX_32 and the NATIVE_POSIX_64 is added, with
both selecting NATIVE_POSIX. This way nothing changes for the existing
native_posix target, allowing it to share almost everything with the
64-bit version.
Both flavors are made available for CI tests to pick them. This assumes
both 32-bit and 64-bit build environments are available.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
My compiler is rather fussy:
zephyr/boards/posix/native_posix/irq_ctrl.c:133:7:
error: conflicting types for ‘hw_irq_ctrl_get_irq_status’
u64_t hw_irq_ctrl_get_irq_status(void)
^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from zephyr/boards/posix/native_posix/irq_ctrl.c:11:
zephyr/boards/posix/native_posix/irq_ctrl.h:29:10:
note: previous declaration of ‘hw_irq_ctrl_get_irq_status’ was here
uint64_t hw_irq_ctrl_get_irq_status(void);
^~~~~~~~~~~~~~~~~~~~~~~~~~
Make the definition match its declaration.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The spi-nor flash nodes require a jedec-id property as per the binding.
We add the jedec-id's as best we can determine based on the data sheets
for the various flash modules on these boards.
However these id's should be validated by actually reading the value to
ensure they are correct.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove whitelisting and enable broader testing on all boards with needed
features.
Add pwm to board yaml where it applies.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Ioannis Glaropoulos