Allow individual specification of the time quanta used for the CAN bus
propagation segment and phase segment 1.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added support for the STM32L496XE series with 512KB internal flash and
256KB SRAM of contiguous addresses.
Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
The DT spec. only has "okay" and not "ok". The Linux kernel has around
12k "okay"s and 300 "ok"s.
The scripts/dts scripts only check for "disabled", so should be safe re.
those at least.
The replacement was done with
git ls-files | xargs sed -i 's/status\s*=\s*"ok"/status = "okay"/'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit adds counter driver based on RTCC module for SiLabs Gecko
SoCs.
Tested with SLWSTK6061A / BRD4250B wireless starter kit.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
stm32wb55rg is a dual core SoC (M4/M0) with a radio/protocol stack
running on M0 core. M0 FW starts at flash address 0x80CB000.
So flash size available to zephyr is 812K instead of 1M.
Configure package size to reflect this (flash size is now 812K)
and update MPU setting to exclude M0 FW. From MPU point of view,
we set flash size to 512K since we should chose a size being a power
of 2.
If we consider there will be 2 images partitions in a FOTA scheme,
512 K is beyond image-0 and hence is sufficient to cover application
image.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
sram2a and sram2b where defined in the prospect of defining
HCI shared memory sections from device tree.
Remove them, since this is not the case anymore.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This adds support for the basic timer counter (TC) found on SAM0
series parts. This driver only supports running the counter
in 32 bit wide mode. Since this mode explicitly slaves the odd
counters to the even ones, only instances of the even ones are
defined.
Tested with tests/drivers/counter/counter_basic_api on SAMD21.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Add support for the Low Power Inter-Integrated Circuit (LPI2C)
controllers found in the NXP Kinetis KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The node name for device_id was device_id@0 it should be
device_id@80a00c to reflect the first register region
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
ARM SysTick peripheral is optional in Cortex-M0 MCUs,
so we delete the respective dts node when the peripheral
is not present.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Atmel SAM D series SoC variants (present in the tree) all have
an ARM Cortex-M0+ core, not a Cortex-M0, so we correct this in
the .dtsi header.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Unlike Cortex-M3 and Cortex-M4, in Cortex-M7 the number of
MPU regions may vary based on the implementation. This commit
adds a DTS node for the ARM MPU peripheral in the device tree
of Cortex-M7 SoCs and updates the fixup files, so we may extract
the number of MPU regions at build time. SoCs:
- nxp_rt
- same70
- stm32f7
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds a DTS node for the ARM MPU peripheral in the
device tree of ARMv8-M SoCs (for the secure and the non-secure
DTS descriptions) and updates the fixup files. SoCs:
- nrf9160
- musca_a
- musca_b1
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Adding missing erase-block-size entries for the flash-controller
nodes in the nrf52810 and nrf52811 .dtsi files.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Move flash-controller and SRAM node definitions under SoC node.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Reduced Kconfig for counter with nRF TIMER and RTC. Added overlays
for TIMER and RTC configuration in the counter test.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This commit adds basic support for nrf52811 in the arch SoC, dts
and nrfx folders.
The nRF52811 is a Bluetooth 5.1 Direction Finding SoC with comprehensive
protocol support.
The nRF52811 SoC is capable of the latest features of Bluetooth 5.1,
the most prominent being Direction Finding.
The radio in the nRF52811 SoC has comprehensive protocol capabilities,
including Bluetooth 5.1 Directing Finding, all Bluetooth 5 features,
802.15.4, Thread, Zigbee, ANT and 2.4 GHz proprietary.
It has 4 dBm TX power and has been optimized to offer the best RX
sensitivity of all SoCs in the nRF52 series.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
add usbd1 definition to rt dts file,
set EHCI controller config default value in rt1050 default config file,
add EHCI controller driver MACROs to dts_fixup.h,
initialize EHCI clock in rt soc.c
add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Dts Nodes for all the GPIO portswere defined. In addition,
a new binding file was created for the gpio driver.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Expose MEC1501 5 I2C/SMB controllers
Add Microchip specific I2C device tree properties
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
All series of stm32 have at least one ADC instance and this commit adds
one ADC node to the root dts file of each soc, and also adds fixing up
mappings to them.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This adds interrupt support to the SAM0 GPIO driver. This is heavily
inspired by @nzmichaelh work in #5715. The primary difference
from that implementation is that here the External Interrupt
Controller (EIC) is separated out into an interrupt controller driver
that is less tightly coupled to the GPIO API. Instead it implements
more of a conversion from the EIC's own odd multiplexing to a more
traditional port and pin mask IRQ-like callback. Unfortunately,
through the EIC on the SAMD2x are relatively well behaved
in terms of pin to EIC line mappings, other chips that share the
peripheral interface are not. So the EIC driver implements a
per-line lookup to the pin and port pair using definitions extracted
from the ASF headers.
The EIC driver still makes some assumptions about how it will be used:
mostly it assumes exactly one callback per port. This should be fine
as the only intended user is the GPIO driver itself.
This has been tested with some simple programs and with
tests/drivers/gpio/gpio_basic_api on a SAMD21 breakout and an
adafruit_trinket_m0 board.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This adds a SERCOM I2C driver for SAM0 series chips.
Tested with a SAMD21 chip on a SSD1306 display and a MLX90393
sensor. Only compile tested for SAMD20 and SAMR21.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Add initial support for the TI CC13x2 / CC26x2 series with the CC2652R
and CC1352R SoCs. The UART and GPIO peripherals are supported. Drivers
use the driverlib HAL from the TI CC13x2 / CC26x2 SDK.
Signed-off-by: Brett Witherspoon <spoonb@cdspooner.com>
Implementation of pinmux for the stm32mp157c_dk2 board.
Some UART pin mux definition has been added (mainly for
UART console and UART/SPI Arduino shield support).
This can be completed with pin mux for other stm32mp157c
UART.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add support for stm32mp1 basic UART API with Zephyr.
UART Console and UART shell are also supported.
Async UART API and USART support is to be done.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Move SERCOM peripherals to use the raw defines generated from DTS
parsing. This adds aliases to the DTS so that the SERCOM number
can still be used for clocking and pinmux.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This adds support for the SAM0 DMA Controller (DMAC). Chained
transfer are not currently implemented.
Tested with tests/drivers/dma/loop_transfer and custom modifications
to that test using three parallel reloading channels. Also tested
with a trivial program that did memory->serial.
Signed-off-by: Michael Hope <mlhx@google.com>
[hageman@inthat.cloud: Rebased and updated commit message]
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Initial support for Microchip MEC1501 series is added to the tree.
Additional support for UART is also included. This SoC supports
two operational modes for interrupts (Direct and Aggregated). For
this commit, the direct capable interrupts are configured in
direct mode.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Henrik Brix Andersen