Provide a preconfigured base address for MMIO and a preconfigured IRQ
pin identifier for the first PCI Ethernet MAC in the Intel Quark X1000
SoC.
Change-Id: I1b527df6c3b1b65da9f0233464e54157029f04f5
Signed-off-by: Michael LeMay <michael.lemay@intel.com>
galileo.c currently calls itself system.c in a comment. It lies.
ia32.c currently calls itself system.c in a comment. Don't believe it.
ia32_pci.c currently calls itself system.c in a comment. It lies.
Change-Id: Icdba074ff2e2e478529bc5757c90b5adbc9dcb8a
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
ioapic_irq_set() needs a vector number: all calls to it now use the
_IRQ_TO_INTERRUPT_VECTOR() macro as expected.
The previous change by which interrupt priorities are now honoured
correctly when connecting ISRs to IRQs statically also changed the way
the interrupt vectors are assigned.
Instead of computing them like this:
interrupt vector ID = IRQ + INT_VEC_IRQ0
They are now determined by a macro:
interrupt vector ID = _IRQ_TO_INTERRUPT_VECTOR(irq)
Change-Id: Icc4576ac9bc6891c8662bcc17a543333eb8745e0
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Configure IOAPIC for Bluetooth interrupts connected to UART.
Change-Id: Iad58f52e95c05245d38dd0f4cb10494b53bad8e0
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
If console handler is defined uart console should also be defined.
Change-Id: I3efcc6c837f8f1621340f7f13bf0603d7dc42fb2
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Only driver specific public headers should be found in include/drivers.
All generic API are found in include/ directory.
Change-Id: Ic50931987bb9460fd4a3843abc6f5de107faf045
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Change all the Intel and Wind River code license from BSD-3 to Apache 2.
Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Since the console is not yet setup, there will be nothing to be printed
out. Also, it adds a dedicated init function which is only useful for
it. Instead, debugging PCI enumeration can be simply done in application
side.
Change-Id: Ia8384caa97d43f0bc4300ecf36bc11d1b8bd5581
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add Kconfig option to specify how interrupt is triggered for SPI.
Also enabling such support for Galileo platform.
Change-Id: Id3112d100089197940f826b827493174d0f22669
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Perform configuration of the shared IRQ has to be done earlier,
as the config code masks the interrupt by default. If configuration
is done after shared_irq_enable() is called, the interrupt is
effectively masked. So move the init level a bit earlier.
Change-Id: Ic7f059628e3cf122d323513e171c7d1a09e5d4a6
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The IOAPIC driver resets all interrupt vectors, so any configuration
has to be done after that. Move the HPET IRQ config to later init
level so we are sure that the configuration is being done.
Change-Id: Id169461cce15252f7fb77e9c07961300233f3344
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With the typos, IRQ triggering conditions are not set correctly.
Change-Id: I0698ce69c3368411a2f91a32ac27608e9f1de252
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
On some platforms (e.g. Galileo), the I2C controller is on PCI bus,
which shares IRQ with other devices (GPIO on Galileo). This patch
adds support for utilizing shared IRQ.
Change-Id: Id4e4714aed37c2893d0ffe9ed1e4edaabb338121
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
On some platforms (e.g. Galileo), the GPIO controller is on PCI bus,
which shares IRQ with other devices (I2C on Galileo). This patch
adds support for utilizing shared IRQ.
Change-Id: I4b44bae15356e4710d54f0343fed1bd27f35e484
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the code to setup the IO-APIC for shared IRQ.
The code to enable shared IRQ with GPIO and I2C will follow.
Change-Id: I6e7de69f83bf7f1dd0da0571dbcb417beb2c232b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The interrupt selectionss are no longer specific to a particular
controller (e.g. I2C_DW_0), but apply to all controllers on
the platform.
[DL: Extracted these changes into their own patch, instead of
being squashed with others. Also modified the Kconfig
options to move them into proper position.]
Change-Id: Idc7ac9769e947447b868dccf772a95dbb5fc8021
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
There are devices that need are part of the architecture core the need
to be initialized prior to devices that are integrated around a core
to make up a complete SOC. Namely the interrupt controller in the SOC
must be configured in order to allow the integrated IP blocks drivers
to initialize correctly.
Change-Id: I0a91e08f98516a7b7dd402ffc6494a071f1326b2
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Michael LeMay