The driver fails to compile when CONFIG_UART_INTERRUPT_DRIVEN=n. This is
due to a nested ifdef on CONFIG_UART_INTERRUPT_DRIVEN that is excluding
pieces of code unrelated to the uart interrupts management.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The PL011 driver is not specific to the cortex_m arch and the driver
does not really use anything from the cmsis header file. Remove it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Creates macros for determining model message lengths based on opcode,
payload length and MIC size. Also adds macro wrapping
NET_BUF_SIMPLE_DEFINE to serve the most common use case.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
DTSpec writes this as a single word, presumably to make it easier to
grep for / more precise. Follow along in the rest of the docs now that
our main DT docs page agrees with this usage.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
The K6X example is part of the wrong subsection (devicetree vs
kconfig) currently. Move it up to the right place (the section which
was recently renamed to "input and output files")
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Re-work the introductory sections of the devicetree documentation,
adding several figures and cross-references to other useful parts of
the documentation.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Device tree overlays are a bit of a stumbling block. Try to add more
cross-references and examples for how to use them to the application
development doc and the west build page.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
When running a ticker node as "must expire", the node would invoke the
ticker callback even when programmed with latency. As "must expire" is
intended for scheduled events which are skipped due to collision, and as
such expected by LLL, purposefully skipped events should not generate
"must expire" callbacks.
Signed-off-by: Morten Priess <mtpr@oticon.com>
Fixes u32_t overflow during intermediary calculations using u64_t for
it. on_off is temporary value used for calculating on and off and it
got overflowed with simple test in tests/drivers/pwm/pwm_api
([period]: 2000, [pulse]: 2000)
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
It is now possible to override a shield variant configuration
for a specific board. Get it documented.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Shields subsystem provides the possibility to override configuration
for boards and to define variants.
Reflect this in documentation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Just housekeeping around the casting between void * arguments to
thread functions and integer types.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
It's possible to have multiple processors configured without using the
SMP scheduler, so don't make definitions dependent on CONFIG_SMP.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
In non-SMP MP situations, the interrupt stacks might not exist, so
do not assume they do. Instead, initialize the TSS IST1 from the
cpuboot[] vector (meaning, on APs, the stack from z_arch_start_cpu).
Eliminates redundancy at the same time.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
When SMP is enabled, the kernel expects that interrupts be delivered
to all CPUs in the system. Change the I/O APIC RTEs accordingly.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This is the Wrong Thing(tm) with SMP enabled. Previously this
worked because interrupts would be re-enabled in the interrupt
entry sequence, but this is no longer the case.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
was ignoring the rest of the expression, though the effect was
harmless (including unreachable code in some builds).
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Trivial change to the Kconfig: the first 32 vectors are reserved,
so it's not possible to have 256 IRQ vectors. Change max to 224.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Add duplicate per-CPU data structures (x86_cpuboot, tss, stacks, etc.)
for up to 4 total CPUs, add code in locore and z_arch_start_cpu().
The test board, qemu_x86_long, now defaults to 2 CPUs.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Take a dummy first argument, so that the BSP entry point (z_x86_prep_c)
has the same signature as the AP entry point (smp_init_top).
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Add a simple inline function and some definitions to faciliate
inter-processor interrupts for SMP initialization/synchronization.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A new 'struct x86_cpuboot' is created as well as an instance called
'x86_cpuboot[]' which contains per-CPU boot data (initial stack,
entry function/arg, selectors, etc.). The locore now consults this
table to set up per-CPU registers, etc. during early boot.
Also, rename tss.c to cpu.c as its scope is growing.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
There's no need to qualify the 64-bit CS/DS selectors, and the GS and
TR selectors are renamed CPU0_GS and CPU0_TR as they are CPU-specific.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
In some places the code was being overly pedantic; e.g., there is no
need to load our own 32-bit descriptors because the loader's are fine
for our purposes. We can defer loading our own segments until 64-bit.
The sequence is re-ordered to faciliate code sharing between the BSP
and APs when SMP is enabled (all BSP-specific operations occur before
the per-CPU initialization).
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This is really just to facilitate CPU bootstrap code between
the BSP and the APs, moving the clear operation out of the way.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
In the general case, the local APIC can't be treated as a normal device
with a single boot-time initialization - on SMP systems, each CPU must
initialize its own. Hence the initialization proper is separated from
the device-driver initialization, and said initialization is called
from the early startup-assembly code when appropriate.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The 32-bit and 64-bit assembly startup sequences share quite a
bunch of common code, so it's factored out into one file to avoid
repeating ourselves (and potentially falling out of sync).
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The linker script was missing symbols that defined the boundaries
of kernel memory segments (_image_rom_end, etc.). These are added
so that core/memmap.c can properly account for those segments.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Elevate the previously 32-bit-only z_x86_prep_c() function to common
code, so both 32-bit and 64-bit arches now enter the kernel this way.
Minor changes to prep_c.c to make it build with the SMP scheduler on.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
And set qemu_x86_long board to build with CONFIG_SMP=y by default.
Apparently two benchmark tests - latency_measure and sys_kernel -
do not work with the SMP scheduler, so those tests are disabled.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This maximum is implicit in the kernel support for SMP, e.g.,
kernel/init.c and kernel/smp.c assume CONFIG_MP_NUM_CPUS <= 4.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Apply same scheme for all nucleo_64 pins boards:
-provide a separate arduino connector dtsi file
-provide complete gpio map
-update board.yaml vs arduino support (i2c, spi and gpio)
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fix CAN loopback mode in the NXP MCUX FlexCAN driver by only disabling
self-reception when loopback mode was not requested.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Try to figure out where the ping reply should be sent if there
are multiple network interfaces in the system.
Fixes#19612
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Carlo Caione