zephyr

Commit Graph

Author	SHA1	Message	Date
Andrew Boie	d4a209d484	nios2: implement irq_offload() For this implementation, the presence of a value in global _offload_routine signifies to the exception code that we should enter the IRQ handling code even if there are no bits enabled in ipending. The 'trap' instruction gets us into the exception handling code. Change-Id: Iac96adba0eaf24b54ac28678a31c26517867a4d2 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>	2016-06-28 15:56:05 -07:00
Andrew Boie	738dec483e	nios2: add static interrupt handling code Supports Internal Interrupt Controller only for now; EIC supoort tracked in ZEP-258. Change-Id: I2d9c5180e61c06b377fce4bda8a59042b68d58f2 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>	2016-06-22 16:42:21 +00:00
Andrew Boie	e2ff2fdd91	nios2: add base exception handling code Change-Id: I56b0ec1a3576a77ca7bd6f2c0217de8053406927 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>	2016-06-22 16:42:20 +00:00

Author

SHA1

Message

Date

Andrew Boie

d4a209d484

nios2: implement irq_offload()

For this implementation, the presence of a value in global
_offload_routine signifies to the exception code that we should
enter the IRQ handling code even if there are no bits enabled
in ipending. The 'trap' instruction gets us into the exception
handling code.

Change-Id: Iac96adba0eaf24b54ac28678a31c26517867a4d2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

2016-06-28 15:56:05 -07:00

Andrew Boie

738dec483e

nios2: add static interrupt handling code

Supports Internal Interrupt Controller only for now; EIC
supoort tracked in ZEP-258.

Change-Id: I2d9c5180e61c06b377fce4bda8a59042b68d58f2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

2016-06-22 16:42:21 +00:00

Andrew Boie

e2ff2fdd91

nios2: add base exception handling code

Change-Id: I56b0ec1a3576a77ca7bd6f2c0217de8053406927
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

2016-06-22 16:42:20 +00:00

3 Commits