Commit Graph

5 Commits

Author SHA1 Message Date
Tanmay Shah 09e2a4e9eb drivers: ipm: add zynqmp r5f support
Add ipm driver to use Inter Processor Interrupts
on Xilinx ZynqMP platform. This patch also adds sample
application that shows use of xlnx ipm driver.

This driver uses default arm gic interrupt controller
and works only for lockstep mode of cortex-r5f
cluster for now.

In split mode the cortex-r5 cluster will
have two r5f cores and they are expected to work in AMP
mode. If both r5f cores run simultaneouly, only one of
the core is able to receive IPI interrupts at this time
and it will be the one that started later. In future
this limitation shall be removed.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
2023-08-15 11:23:04 +00:00
Piotr Wojnarowski fc29f73a29 soc: arm: xilinx_zynqmp: Move GIC version to DT
Move the GIC version to the device tree for xilinx_zynqmp
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Kumar Gala 4aae32640f dts: arm/arm64: remove DTS 'label' property requirement from gic and timer
The armv8 timer, arm gic, and arm gic-v3-its don't use or need the
devicetree label property.  Update the dts bindings to not require it and
remove setting of the label property in dts files.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-06-16 09:48:12 -05:00
Stephanos Ioannidis 38f0b05b99 dts: xilinx_zynqmp: Fix incorrect RPU device tree specification.
This commit fixes the following problems with the RPU device tree:

1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not
  Cortex-R4.

2. RPU and APU use different interrupt controllers (PL390 GICv1 and
  GIC-400 GICv2, respectively) mapped to the same CPU local bus address
  region but with different offsets for the distributor and CPU
  interrupt control register sets. The GIC address mapping specified by
  the current dts is that of an APU and does not apply to the PL390
  GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register
  Reference" document from Xilinx for more information).

For more details, refer to the issue #20217.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-07 17:17:12 +01:00
Stephanos Ioannidis 8a29685a25 dts: xilinx_zynqmp: Refactor dts to specify RPU and APU separately.
ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and
Cortex-A for APU.

Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within one project, the RPU and APU should be considered
separate platforms.

This commit relocates the device tree nodes that are not common between
RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi).

When Cortex-A53 APU support is added in the future, an additional dtsi
file (zynqmp_apu.dtsi) for specifying the APU device tree should be
added.

For more details, refer to the issue #20217.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-07 17:17:12 +01:00