It's worth using custom timing information on a few systems to save
cycles or gain precision. But make the use of k_cycle_get_32() a
proper default instead of hardcoding all the platforms and failing to
build on new ones. On Xtensa and RISC-V (and now x86_64) the cycle
informatoin from that call is a very fast wrapper around the native
counters anyway -- all you would save would be the function call
overhead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These files were relying on _thread_essential_set() from
kernel_internal.h, but not including it directly. New architectures
won't transitively include things the same way.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
I was half way through typing up my own one of these when I realized
there was one already in the tree. Move it to a shared header.
(FWIW: I really doubt that most architectures actually benefit from
their own versions of these tools -- GCC's optimizer is really good,
and custom assembly defeats optimization and factorizations of the
expressions in context.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The HPET default is to deliver events on the same INTIn as the legacy
PIT IRQ, and in fact our code requires that because it uses the
"legacy routing" option. So this isn't really a configurable and has
to be set correctly. Do it right in the kconfig default instead of
forcing boards to set it.
(No, I have no idea where "20" came from either.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This was apparently intended to allow for per-arch linker includes,
but no such includes ever existed. All it does is senselessly throw
an error on unrecognized architectures. Yank.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These files were using z_thread_malloc() without including
kernel_internal.h. On existing architectures that works due to
transitive includes, but x86_64 has a thinner include layer and
doesn't do it for us. Include the files required for the APIs we use.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Fix the QSPI and hyperflash nodes to be proper SPI children and expose
the address range for direct access as part of the controller's reg
region.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We need to refactor how we determine CONFIG_FLASH_{SIZE,BASE_ADDRESS}
for when we have a QSPI that is memory mapped. "zephyr,flash" is going
to point the actual flash component that will be on a SPI bus and thus
the device node's reg property tells us which CS on the SPI bus its on,
not the memory mapped address/size of the flash.
So we make a few assumptions to handle this case:
1. If the #size-cells for the flash node is 0, we assume its a QSPI
memory mapped flash
2. That the QSPI memory mapped node (parent of what "zephyr,flash" is
point to, will contain a reg propery where the second reg pair will
be the memory mapped region for the flash.
We move handling of CONFIG_FLASH_{SIZE,BASE_ADDRESS} into flash.extract
so its all in one place.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Make the documentation page a little bit more interesting with top-level
navigation grid highlighting the most important sections with a brief
description.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add Accelerometer mouse by using fxos8700 accelerometer and using data
to control USB HID mouse.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
move development model from the wiki to the main documentation to keep
it in sync and updated all the time and to get proper reviews.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The CIAA and QFAB variants of the nRF52832 were missing in Kconfig,
although present in Device Tree. Add the relevant Kconfig entries in
order to be able to select them.
Fixes#12417
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
When used suitable config overlay, qemu_cortex_m3 with Ethernet
support can be started with just usual "make run".
An example of such overlay is included with samples/net/echo_server,
can be built and run with:
make BOARD=qemu_cortex_m3 \
CONF_FILE="prj.conf overlay-qemu_cortex_m3_eth.conf" run
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Add support for the TRNG device contained in the i.MX RT SoCs. It uses
the existing MCUX driver, and mostly consists in adding the Kconfig and
DTS entries.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Instead of getting the base address from the MCUX headers, use the base
address from the device tree.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The original implementation of gpio functions access registers
directly. Using LL library can add a set of unifying access
functions for all series of stm32 for avoiding accessing low level
code, and improve readability.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
All series STM32 have mostly the same GPIO architecture
and can share the same code for GPIO manipulation.
Functions of the external interrupt line control are also the same.
This patch extracts common code from them and put them into the 'common'
folder.
Functions of control GPIO of these series scattered in
soc/arm/st_stm32/stm32xx/ folders contain these functions:
stm32_gpio_flags_to_conf(), stm32_gpio_configure(), stm32_gpio_set(),
stm32_gpio_get, stm32_gpio_enable_int().
This patch merges them into the gpio_stm32.c file.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Connecting to a non-open port causes connect() to hang forever.
This patch releases connect() to return error to the caller.
Signed-off-by: Björn Stenberg <bjorn@haxx.se>
Adds documentation-commentary to some infrastructure used by the LL.
It is a long-term effort to better document the LL.
Notably ticker and mayfly require more documentation; this will be
done later.
Signed-off-by: Mark Ruvald Pedersen <mped@oticon.com>
Added macro that generates simple report descriptor for mouse.
This improves the readability of hid-mouse sample.
Signed-off-by: Marcin Szymczyk <Marcin.Szymczyk@nordicsemi.no>
It may happen that panic occured while logger backend
was formatting output data. In that case output buffer
could get corrupted as logger assumes that processing
happens in one context only (panic is the only exception).
Added log output buffer flushing on entering panic state.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
* i2c, spi, gpio are not tested, remove them now.
* fix the license issue in openocd.cfg
* fix the shell related setting
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
1. optimize the baudrate calulation
2. For arc iot soc, the interval val is 4
3. before write any regs, the clk of uart must be enabled
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
The initial support of iotdk which is a board based on Synopsys
ARC IoT SoC.
In this commit, it includes
* processor support
* UART driver
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
The mimxrt1020_evk and mimxrt1060_evk boards had invalid jlink device
names. Debugging via 'ninja debug' now works on these boards.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Commit 76b3518ce6 ("kernel: Make statements evaluate boolean
expressions") changed the type of is_polling in the struct _poller
from int to bool. In the conversion a "0" has been changed into "true"
instead of "false". Fix that.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Adds support for the device configuration data (DCD), which provides a
sequence of commands to the imx rt boot ROM to initialize components
such as an SDRAM.
It is now possible to use the external SDRAM instead of the internal
DTCM on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk. Note,
however, that the default board configurations still link data into
internal DTCM, therefore you must use a device tree overlay to override
"zephyr,sram = &sdram0"
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Fixes a Kconfig typo in the mimxrt1060_evk board that was introduced
when the board was split into separate hyperflash and qspi
configurations.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Moves the default TEXT_SECTION_OFFSET from the board level to the soc
level for the imx rt series. This offset is used to reserve space for
the imx boot header for external xip flash images.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds support for the boot data, image vector table, and FlexSPI NOR
config structures used by the imx rt boot ROM to boot an application
from an external xip flash device.
It is now possible to build and flash a bootable zephyr image to the
external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and
mimxrt1060_evk boards via the 'ninja flash' build target and jlink
runner. Note, however, that the default board configurations still link
code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y
or CONFIG_CODE_QSPI=y explicitly to override the default. You must also
set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the
image.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Use the page size retrieved via page layout in flash erase
shell command in case erase size is not given.
Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
Driver update to use GPIO driver for the reset control signal.
Driver update to use definitions from DTS including I2C address.
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
Update Kconfig for tlv320dac audio DAC to include GPIO
as a dependency. The codec driver now uses GPIO driver
to control the RESET for the DAC.
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
Add the codec reset GPIO to intel_s1000_crb's DTS
Update the DTS fixup for intel_s1000_crb accordingly
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
Andy Ross