Commit Graph

242 Commits

Author SHA1 Message Date
Sathish Kuttan 39570b5bae soc: intel_s1000: Add SoC routine for GNA power-up
Add an SoC level routine to turn power and clock on for
Intel GNA block in Intel S1000 SoC.

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-01-14 08:43:51 -05:00
Andy Ross b69d0da82d arch/x86_64: New architecture added
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().

The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.

Limitations:

+ Right now the SDK lacks an x86_64 toolchain.  The build will fall
  back to a host toolchain if it finds no cross compiler defined,
  which is tested to work on gcc 8.2.1 right now.

+ No x87/SSE/AVX usage is allowed.  This is a stronger limitation than
  other architectures where the instructions work from one thread even
  if the context switch code doesn't support it.  We are passing
  -no-sse to prevent gcc from automatically generating SSE
  instructions for non-floating-point purposes, which has the side
  effect of changing the ABI.  Future work to handle the FPU registers
  will need to be combined with an "application" ABI distinct from the
  kernel one (or just to require USERSPACE).

+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
  of all memory.  No MMU/USERSPACE support yet.

+ We are building with -mno-red-zone for stack size reasons, but this
  is a valuable optimization.  Enabling it requires automatic stack
  switching, which requires a TSS, which means it has to happen after
  MMU support.

+ The OS runs in 64 bit mode, but for compatibility reasons is
  compiled to the 32 bit "X32" ABI.  So while the full 64 bit
  registers and instruction set are available, C pointers are 32 bits
  long and Zephyr is constrained to run in the bottom 4G of memory.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-01-11 15:18:52 -05:00
Carles Cufi cee87a1ca2 soc: nrf: Add missing nRF52832 variants
The CIAA and QFAB variants of the nRF52832 were missing in Kconfig,
although present in Device Tree. Add the relevant Kconfig entries in
order to be able to select them.

Fixes #12417

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2019-01-11 10:32:42 +01:00
Aurelien Jarno 074f8a0a26 soc: nxp_imx: Add support for TRNG
Add support for the TRNG device contained in the i.MX RT SoCs. It uses
the existing MCUX driver, and mostly consists in adding the Kconfig and
DTS entries.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-10 21:22:15 -06:00
Song Qiang 2fb616efbe soc: arm: st_stm32: Using LL library to implement gpio functions
The original implementation of gpio functions access registers
directly. Using LL library can add a set of unifying access
functions for all series of stm32 for avoiding accessing low level
code, and improve readability.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
2019-01-10 13:09:19 -06:00
Song Qiang 9612f9d840 soc: arm: st_stm32: Cleanup gpio function code.
All series STM32 have mostly the same GPIO architecture
and can share the same code for GPIO manipulation.
Functions of the external interrupt line control are also the same.
This patch extracts common code from them and put them into the 'common'
folder.

Functions of control GPIO of these series scattered in
soc/arm/st_stm32/stm32xx/ folders contain these functions:
stm32_gpio_flags_to_conf(), stm32_gpio_configure(), stm32_gpio_set(),
stm32_gpio_get, stm32_gpio_enable_int().
This patch merges them into the gpio_stm32.c file.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
2019-01-10 13:09:19 -06:00
Wayne Ren 6b5dea578e board: iotdk: bug fixes and remove unsupported drivers config
* i2c, spi, gpio are not tested, remove them now.
* fix the license issue in openocd.cfg
* fix the shell related setting

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-01-10 07:05:51 -05:00
Wayne Ren 163625cf78 board: iotdk: necessary clean up based on latest master branch
* clean up the DTS related definitions
* code cleanup
* do the tests/kernel sannity check

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-01-10 07:05:51 -05:00
Wayne Ren 022f061632 board: add the initial support of iotdk
The initial support of iotdk which is a board based on Synopsys
ARC IoT SoC.

In this commit, it includes

* processor support
* UART driver

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-01-10 07:05:51 -05:00
Maureen Helm a9389da038 soc: nxp_imx: Add support for device configuration data (DCD)
Adds support for the device configuration data (DCD), which provides a
sequence of commands to the imx rt boot ROM to initialize components
such as an SDRAM.

It is now possible to use the external SDRAM instead of the internal
DTCM on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk. Note,
however, that the default board configurations still link data into
internal DTCM, therefore you must use a device tree overlay to override
"zephyr,sram = &sdram0"

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-09 16:01:25 -06:00
Maureen Helm b5551d0690 soc: boards: Reserve space for the imx boot header at the soc level
Moves the default TEXT_SECTION_OFFSET from the board level to the soc
level for the imx rt series. This offset is used to reserve space for
the imx boot header for external xip flash images.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-09 16:01:25 -06:00
Maureen Helm 8e3004953d soc: nxp_imx: Add support for external xip flash boot header
Adds support for the boot data, image vector table, and FlexSPI NOR
config structures used by the imx rt boot ROM to boot an application
from an external xip flash device.

It is now possible to build and flash a bootable zephyr image to the
external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and
mimxrt1060_evk boards via the 'ninja flash' build target and jlink
runner. Note, however, that the default board configurations still link
code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y
or CONFIG_CODE_QSPI=y explicitly to override the default. You must also
set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the
image.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-09 16:01:25 -06:00
Ryan QIAN b416758e9f arch: arm: nxp: imxrt1021: add device support
- Add Soc information for RT1020

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-09 11:39:31 -06:00
Ryan QIAN e66e6b054c soc: nxp_imx: rt: fix enet pll initialization config macro name
- Update config macro name for enet pll
- Update impacted defconfig of RT1052

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-09 11:39:31 -06:00
Piotr Mienkowski 9f84889779 soc: same70: Add SWO logger support
This commit configures ETM/TPIU clock upon startup in case SWO logger
backend is enabled on Atmel SAM E70 SoC.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-01-09 15:30:59 +01:00
Christian Taedcke e6d5c4e3da soc: silabs_exx32: Add SWO logger support to EFM32PG12B
By default, after reset SWO signal is not connected to GPIO pin.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-01-09 15:30:59 +01:00
Piotr Mienkowski 8bed2d5e27 soc: silabs_exx32: Add SWO logger support
By default, after reset SWO signal is not connected to GPIO pin. This
commit adds required initialization code to enable support for SWO
logger. Not all SoC series support the feature.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-01-09 15:30:59 +01:00
Piotr Mienkowski 03eaafddfd logger: add a SWO backend
This commit adds Serial Wire Output (SWO) logger backend. SWO is an
extension of Serial Wire Debug (SWD) port developed by ARM.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-01-09 15:30:59 +01:00
Erwan Gouriou f5d48240e9 drivers/gpio: stm32l4: PortG[15:2] requires dedicated VDDio2
On STM32L4, 14 pins (Port G[15:2]), require external power supply.
Activate this at port G init when PWR_CR2_IOSV is defined.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-01-09 08:05:24 -06:00
Andrei Gansari f6d3f6b92b mimix1050rt: gPTP build fix
Sets iMX RT's cmake and fixup to enable gPTP in MCUX_ETH.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-09 07:57:18 -06:00
Piotr Mienkowski aa2c27d007 soc: silabs_exx32: Add independent Kconfig options for HAL libraries
Zephyr gecko drivers depend on libraries provided by the vendor. The
same libraries may also be used directly by the application code or
RAIL library. To facilitate the latter use case scenario this commit
adds Kconfig options to independently enable compilation of vendor
HAL library modules.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-01-08 13:31:42 -06:00
Ashokkumar B 3c00d955f3 drivers: gpio: Add DTS support for Stellaris gpio driver.
* Add DTS support for gpio controller driver

Signed-off-by: Ashokkumar B <ashokkumar@zilogic.com>
Signed-off-by: Subash G <subash@zilogic.com>
Signed-off-by: Vishnu K <vishnu@zilogic.com>
Signed-off-by: Vaishnavi D <vaishnavi.d@zilogic.com>
2019-01-08 13:30:26 -06:00
Piotr Mienkowski 973af2c8d7 dts: silabs: use 'aliases' to remove dts_fixup defines
By adding 'aliases' node in SoC .dtsi file it is possible to generate
DT_ defines which specify a logical name rather than relay on module
location on APB bus. E.g. DT_SILABS_GECKO_USART_40010000_LABEL becomes
DT_SILABS_GECKO_USART_USART_0_LABEL. Thus it is possible to remove
dts_fixup.h defines.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-01-08 11:56:02 -06:00
Sathish Kuttan c3da9238f1 soc: intel_s1000: add DMIC power control
Add DMIC power on to SoC init sequence

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-01-07 16:50:49 -05:00
Flavio Ceolin 359adfc959 soc: arm: Make statements evaluate boolean expressions
MISRA-C requires that the if statement has essentially Boolean type.

MISRA-C rule 14.4

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2019-01-07 08:52:07 -05:00
Flavio Ceolin 353933125f soc: x86: Make statements evaluate boolean expressions
MISRA-C requires that the if statement has essentially Boolean type.

MISRA-C rule 14.4

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2019-01-07 08:52:07 -05:00
Maureen Helm 6876dc71c1 soc: nxp_imx: Fix ethernet build error
Fixes an ethernet build error introduced with MCUXpresso SDK 2.5.0,
caused by a slight change in the ethernet pll configuration structure.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-04 14:35:35 -05:00
Erwan Gouriou 7f4eda501a dts: stm32f1: add uart5
Add uart5 nodes to stm32f1 series dts.
Provide matching dts_fixup add-on.

Signed-off-by: Chen Han <qq1433255094@outlook.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-01-04 10:07:54 -06:00
Maureen Helm 011a88c744 ext: mcux: Update to MCUXpresso SDK 2.5.0
Updates the MCUXpresso SDK to version 2.5.0 for applicable SoCs.
Wireless (KW*) and legacy (KL25) SoCs were not included in this
MCUXpresso SDK release and are therefore not updated here.

New in this release is SoC-level and board-level support for external
xip flash in the i.MX RT family.

For RT1050, we are now using the MCUXpresso SDK for the EVKB version of
the board, which correponds to an upgrade from A0 to A1 silicon.
However, we don't yet have Kconfigs in place to support A1 silicon part
numbers, and therefore add a simple cmake hack to convert A0 part
numbers to A1 part numbers.

The SDK flash driver interface also changed slightly in this release,
and thus the zephyr flash shim driver is updated accordingly.

Origin: MCUXpresso SDK
License: BSD 3-Clause
URL: mcux.nxp.com
Purpose: Provide device header files and bare metal peripheral drivers
for Kinetis, LPC, and i.MX SoCs.
Maintained-by: External

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-03 17:25:28 -05:00
Loic Poulain 85b8a6b84b clock_control: stm32: Add support for MSI PLL MODE
Add support for Low Speed External 32.768 kHz oscillator (LSE ).
Add support for MSI PLL-Mode offering an automatic calibration feature
in combination with the LSE. This allows the MSI to reach an accurate
+/-0,25% clock perfectly suitable for USB full-speed clock.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-01-02 09:33:21 -05:00
Peter A. Bigot 1c5cd92e12 soc: nordic: default GPIO when SPI enabled
SPI devices almost always require chip selects, which are configured
through GPIOs.  Make the GPIO infrastructure available by default when
SPI is enabled.

Signed-off-by: Peter A. Bigot <pab@pabigot.com>
2019-01-02 13:01:41 +01:00
Anas Nashif 74a74bb6b8 power: rename api sys_soc -> sys_
sys_soc is just redundant, just call APIs with sys_*.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-12-28 16:16:28 -05:00
Anas Nashif 9151fbebf2 power: rename APIs and removing leading _
Remove leading underscore from PM APIs. _ was used for internal APIs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-12-28 16:16:28 -05:00
Ioannis Glaropoulos c8ff1fd27f soc: nordic: add Kconfig options for several peripherals
In the wake of introducing nRF9160 .dtsi header, we are
adding several HAS_HW_NRF_xxxx Kconfig symbols, for the
peripherals present in nrf9160 SoC.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-12-21 21:03:55 +01:00
Andrzej Głąbek 4b43065cfc drivers: nrf: Enable nRF drivers by default in Kconfig
Make the following nRF peripheral drivers:
- ADC
- GPIO
- I2C
- SPI
- UART
- USB_DEVICE
enabled by default so that users do not need to explicitly enable them
in their applications after choosing an nRF SoC as the build target.

Kconfig options enabling these drivers depend on both a given hardware
feature (e.g. I2C) and an nRF family SoC selected, so effectively they
will be automatically enabled only when it is adequate (and in most
cases these drivers are the only option for a given hardware feature
on nRF SoCs).

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-12-21 21:01:37 +01:00
Andrzej Głąbek 7c13ba9965 drivers: serial: nrf: Remove false dependency on the gpio driver
Implementations of both flavors of serial drivers for Nordic SoCs
are no longer dependent on the gpio driver. Remove the dependency
from Kconfig.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-12-21 21:01:37 +01:00
Mieszko Mierunski 4a4e51ffa7 drivers: nrf: Fix UARTE fixup defines.
Due to alias changes, after UARTE is enabled current dts_fixup
is not working.

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2018-12-20 18:32:40 +01:00
AJ Palmer 2f04dc69c0 boards: arm: nucleo_f756zg: Created new board and soc definition
Added board definitions for nucleo_f756zg. Features include gpio,
pinmux, uart (ST Zio, ST-Link and Arduino Uno v3 interfaces).

Added basic documentation and some soc definitions for the
stm32 f756XX soc.

Signed-off-by: AJ Palmer <ajpcode@hotmail.com>
2018-12-17 11:35:27 -06:00
Kumar Gala cca5b61e84 arc: cleanup linker scripts to include autoconf.h first
The various linker scripts on arc would include autoconf.h in the arch
linker script but might have CONFIG_ symbols referenced in the soc
specific linker script.  Move autoconf.h inclusion to top of the soc
specific linker script out of the arch specific one so we know
autoconf.h is seen before any CONFIG_ references.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-12-17 10:08:02 -06:00
Maureen Helm ac562d537b soc: arm: Don't touch interrupts in kinetis watchdog init
The early boot watchdog init for kinetis was incorrectly disabling and
reenabling interrupts to preserve timing during the unlock sequence.
However, interrupts are already disabled before this routine executes
and the kernel is not yet ready to enable them when this routine exits.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-17 08:26:30 -06:00
Aurelien Jarno 6752b5df3f drivers: flash: add driver for STM32F7x series
This patch adds a flash driver for the STM32F7x series, inspired from
the STM32F4x one. It has been tested on the STM32F723, but should also
work on other SoCs of the family.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-12-17 08:15:59 -06:00
Vincenzo Frascino d82fb80781 dts: arm: Code Cleanup in v2m_beetle
This patch cleans up the code in the recently added dts_fixup.h,
restoring the original alignment of the file.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2018-12-14 07:24:48 -06:00
Vincenzo Frascino 93088f4f8f dts: arm: Fix Dual Timer IRQ config for v2m_beetle
The dts.fixup for v2m_beetle contains a wrong setting for the IRQ fixup
for the Dual Timer IRQ.

This patch fixes the symbol included in the generated header.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2018-12-14 07:24:48 -06:00
AJ Palmer bd8f15f555 stm32: dts: f7: added i2c4 node
Added i2c4 node to stm32f746.dtsi for stm32f74+ socs.
Added device tree fixup for i2c4.

Signed-off-by: AJ Palmer <ajpcode@hotmail.com>
2018-12-14 07:22:51 -06:00
Piotr Mienkowski 74cb5f9728 soc: silabs_exx32: Simplify Kconfig options
This commit simplifies Kconfig options related to handling SoC series,
part numbers. This is a first step required to add remaining part
numbers to the existing configuration.

This change is possible since all SiLabs SoCs within a single series
have a very uniform structure.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2018-12-13 12:59:27 -06:00
Manivannan Sadhasivam f8ac865693 arm: stm32f4: Add UART4 pinmux definitions
Add missing UART4 pinmux definitions for STM32F4 series.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-12-13 08:07:28 -06:00
Rajavardhan Gundi 4df8ba3fe0 linker: intel_s1000: Remove limits on code and data sections
All text, data and bss sections are all mapped to the same physical
memory (SRAM). This patch removes the individual section limits
and defines a common limit for the sum of text, data and bss sections.
This would make it more flexible for application developers.

Fixes #11268.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-12-10 22:05:06 -05:00
Wayne Ren 64522df740 soc: arc: clean up the timer relatted definitions
the old definitions are not required

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-12-07 17:08:15 -05:00
Endre Karlson 91c4d20214 arm: silabs: Enable DCDC before setting up clk
This enables DCDC for Silabs devices before initializing the
clock.

Signed-off-by: Endre Karlson <endre.karslon@gmail.com>
2018-12-07 13:55:31 -06:00
Adithya Baglody 9f416da751 soc: ti_simplelink: cc32xx: soc.h: Incorrect enum definition.
Instead of creating an typedef enum it was creating an object.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-12-07 10:32:41 -05:00