We no longer use a page pool to draw memory pages when doing
memory map operations. We now preallocate the entire virtual
address space so no allocations are ever necessary when mapping
memory.
We still need memory to clone page tables, but this is now
expressed by a new Kconfig X86_MAX_ADDITIONAL_MEM_DOMAINS
which has much clearer semantics than specifying the number
of pages in the pool.
The default address space size is now 8MB, but this can be
tuned by the application.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Just tell the kernel that RAM starts 1MB in, period.
Better simulation of a low-memory microcontroller as
we're not managing a very large number of page frames
we'll never use.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
test i2c api on microchip mec15xxevb_assy6853 board by writing
and reading data with nxp pca95xx device on board.
Signed-off-by: peng1 chen <peng1.chen@intel.com>
This allows to get much more reproducible results in terms of
amount of tests passed & failed.
But note it requires QEMU for ARC with icount support!
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
When zefi.py was changed to pass compiler and objcopy the flag to
objcopy for the EFI target was dropped. This is because the current
SDK (0.12.1) doesn't support that target type for objcopy. However,
target is necessary for the images to be created correctly and boot.
Switch back to use the host objcopy as a stop gap fix, until the SDK
can support target for EFI.
Fixes: #31517
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Enables the FlexSPI NOR flash driver, configures the FlexSPI pins, and
updates the board documentation accordingly on the mimxrt1064_evk.
Note that this SoC has two FlexSPI instances: one instance has an
in-package QSPI flash used for XIP; the other instance has a board-level
QSPI flash used for storage, not XIP. This patch enables the flash
driver on the non-XIP flash only.
Tested with:
- samples/subsys/fs/littlefs
- samples/drivers/flash_shell
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
boards: arm: Rename flexspi_qspi to flexspi_nor for mimxrt1064_evk
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Reworks the NXP FlexSPI device tree bindings to configure controller and
device properties needed for an upcoming FlexSPI flash driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Cleans up the HyperFlash device tree nodes on the mimxrt1050_evk and
mimxrt1060_evk_hyperflash boards to be more consistent with other
FlexSPI child nodes.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Remove conditionals (PM_DEEP_SLEEP_STATES and PM_SLEEP_STATES) from
power management code. Now these features are always available when
power management is enabled.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Migrate the whole pm subsystem to use new power states information
from power_state.h and get states and residency properties from
device tree.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
TICKLESS_CAPABLE is now selectable only and without prompt, so remove it
from _defconfig files and select it directly by the timer.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We no longer use a page pool to draw memory pages when doing
memory map operations. We now preallocate the entire virtual
address space so no allocations are ever necessary when mapping
memory.
We still need memory to clone page tables, but this is now
expressed by a new Kconfig X86_MAX_ADDITIONAL_MEM_DOMAINS
which has much clearer semantics than specifying the number
of pages in the pool.
The default address space size is now 8MB, but this can be
tuned by the application.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Just tell the kernel that RAM starts 1MB in, period.
Better simulation of a low-memory microcontroller as
we're not managing a very large number of page frames
we'll never use.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add board support files for mimxrt1024_evk, the development board for
i.MXRT1024(CM7) SoC.
- Add pinmux, dts, doc.
- Code can be loaded to SRAM.
- Tested samples: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add LED and switch DTS information. Port P0 received the NVIC line 20
on Cortex-M0+ cpu. This way, SW_0 switch can be connected as external
interrupt source for both m0 and m4 cpus.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add LED and switch DTS information. Port P0 received the NVIC line 20
on Cortex-M0+ cpu. This way, SW_0 switch can be connected as external
interrupt source for both m0 and m4 cpus.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add an emulation controller which routes eSPI traffic to attached
emulators depending on the selected chip(mostly host).
This allows drivers for eSPI peripherals to be tested on systems
that don't have that peripheral attached, with the emulator handling
the eSPI traffic.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Currently, zefi.py takes host GCC OBJCOPY as
default. Fixing the script to use CMAKE_C_COMPILER
and CMAKE_OBJCOPY.
Fixes: #27047
Signed-off-by: Spoorthy Priya Yerabolu <spoorthy.priya.yerabolu@intel.com>
Currently configuration for STM32F746G Discovery board on reset-start
event is inherited from included files (OpenOCD stm32f7x.cfg), but
contrary to the inherited adapter speed on reset-init event, the speed
inherited for the reset-start event is only 2000 kHz, which is not
available, so a lower speed is picked up automatically generating the
following message several times when flashing the board:
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
That commit overrides that suboptimal speed for reset-start event and
sets it to the same speed as used by reset-init event, i.e. the maximum
speed (4000 kHz), so the noisy messages like the above one disappear.
The change also improves a bit the throughput when writing to the board.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
This change enables support for KSZ8794 DSA device on the ip_k66f
board. Each LAN port is defined as a DTS subnode.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch adds Kconfig entries to nRF5340-DK description that
automatically configure RPMsg Service if it is enabled for the build.
Co-authored-by: Piotr Szkotak <piotr.szkotak@nordicsemi.no>
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
When using Slim Bootloader the UART configuration isn't quite the same
as with the UEFI BIOS. In particular, UART2 is hidden in PCIe and is
instead accessible using a fixed MMIO address. Interrupts are also not
supported for this UART currently.
The simplest way to create builds against this special BIOS/bootloader
setup seems to be to create a new board variant/definition which lets
us provide a custom device tree overlay as well a dedicated Kconfig
default configuration.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The bt-uart, uart-pipe and bt-mon-uart DT chosen values are all
Bluetooth specific. Since Bluetooth isn't supported on the ehl_crb
board currently just remove these.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This CL provided an example of how turns on the low-voltage level
detection feature in npcx series. It demonstrates enabling low-voltage
level detection of I2C1_0 SCL/SDA io-pads if the power rail of their PUs
is 1.8V.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Firmware implementing the PSCI functions described in ARM document
number ARM DEN 0022A ("Power State Coordination Interface System
Software on ARM processors") can be used by Zephyr to initiate various
CPU-centric power operations.
It is needed for virtualization, it is used to coordinate OSes and
hypervisors and it provides the functions used for SMP bring-up such as
CPU_ON and CPU_OFF.
A new PSCI driver is introduced to setup a proper subsystem used to
communicate with the PSCI firmware, implementing the basic operations:
get_version, cpu_on, cpu_off and affinity_info.
The current implementation only supports PSCI 0.2 and PSCI 1.0
The PSCI conduit (SMC or HVC) is setup reading the corresponding
property in the DTS node.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The IIS2DLPC drdy interrupt can be routed to either INT1 or
INT2 pin. Currently the selection is done by Kconfig configuration.
This commit is instead moving it into Device Tree as 'drdy-int'.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The BBC micro:bit v2 is a mini-computer that has been
designed to make the coding fun and easy to learn.
The micro:bit v2 is completely programmable so you can
easily bring your ideas to life! From making games to
creating music and even controlling robots.
The micro:bit comes with neat hardware such as a 25 LED
display, buttons, in-built speakers, Bluetooth 5 & Mesh
connectivity and sensors for temperature, motion & light.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Upgrade board specification to use the VirtIO board.
Keeps FPU run-time support disabled since the RISC-V 64-bit FPU
support in kernel appears to be non-functional.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Andrew Boie