Commit Graph

17 Commits

Author SHA1 Message Date
Gerard Marull-Paretas e81e92dbb9 boards: convert images to JPEG and reduce image size
The boards folder uses ~142.8 MB, being the largest in the repository.
This is due mostly to board images, which are in most cases not
optimized for web content. This patch tries to address this problem by
converting all pictures to JPEG (quality 75) and by adjusting its size
up to 750 px (the width of the documentation content). Images that
specified a fixed width in rst files are converted down to that value
instead.

With this patch, folder goes down to ~53.5 MB from 142.8 MB (-~63%).
Note that this patch introduces a new set of binary files to git
history, though (bad).

The process has been automated using this quickly crafted Python script:

```python
from pathlib import Path
import re
import subprocess

def process(doc, image, image_jpeg, size):
    subprocess.run(
        (
	     f"convert {image}"
	     "-background white -alpha remove -alpha off -quality 75"
	     f"-resize {size}\> {image_jpeg}"
	),
        shell=True,
        check=True,
        cwd=doc.parent,
    )
    if image != image_jpeg:
        (doc.parent / image).unlink()

for doc in Path(".").glob("boards/**/*.rst"):
    with open(doc) as f:
        content = ""
        image = None
        for line in f:
            m = re.match(r"^(\s*)\.\. (image|figure):: (.*)$", line)
            if m:
                if image:
                    process(doc, image, image_jpeg, size)

                image = Path(m.group(3))
                if image.suffix not in (".jpg", ".jpeg", ".png"):
                    content += line
                    image = None
                    continue

                image_jpeg = image.parent / (image.stem + ".jpg")
                size = 750
                content += (
                    f"{m.group(1)}.. {m.group(2)}:: {image_jpeg}\n"
                )
            elif image:
                m = re.match(r"\s*:height:\s*[0-9]+.*$", line)
                if m:
                    continue

                m = re.match(r"\s*:width:\s*([0-9]+).*$", line)
                if m:
                    size = min(int(m.group(1)), size)
                    continue

                content += line
                if line == "\n":
                    process(doc, image, image_jpeg, size)
                    image = None
            else:
                content += line

    with open(doc, "w") as f:
        f.write(content)
```

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-29 10:18:18 +02:00
Anas Nashif 798a552daf boards: intel_s1000_crb: remove board/soc
Remove the intel_s1000_crb board. it is no longer available or supported
in the zephyr tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-06-13 16:19:51 -04:00
Anas Nashif 79649de781 doc: fix references for xt-sim
Fix missing file and sample references.

Fixes #19661

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-26 09:43:57 -07:00
Kumar Gala 1dc4b1dd2f boards: shrink image sizes
Reduce images sizes of boards.  Get a roughly 3x reduction in size.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-02-07 13:52:45 -05:00
Ulf Magnusson 984bfae831 global: Remove leading/trailing blank lines in files
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.

Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.

Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-12-11 19:17:27 +01:00
Andrew Boie 6fd6b7e50a xtensa: remove legacy arch implementation
We re-wrote the xtensa arch code, but never got around
to purging the old implementation.

Removed those boards which hadn't been moved to the new
arch code. These were all xt-sim simulator targets and not
real hardware.

Fixes: #18138

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-12 01:26:34 -04:00
David B. Kinder 505cc2bb0e doc: use :zephyr_file: where appropriate
A new role :zephyr_file: is available that renders to a link to the file
or folder in GitHub.  Find appropriate references using :file: and
convert to :zephyr_file: to take advantage of its linking capability.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2019-03-09 09:50:27 -05:00
Anas Nashif acaae579cc doc: boards: make board images consistent with board name
Having the image use the same name will help us script listing the
boards.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-02-10 17:48:08 -05:00
Anas Nashif 0e4ff809d7 doc: boards: move all board docs to be index.rst
Be consistent in how board docs are named and move all to index.rst.
This will make the URL to the board documentation predictable and easier
to remember.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-02-09 17:22:08 -06:00
Anas Nashif 28b2f32967 boards: fix intro text for many boards
The phrase "Zephyr applications use the ..." in many boards and
inconsistently. This is just to say what is the board identify is.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-02-09 17:22:08 -06:00
Anas Nashif cea0b3a9c2 xtensa: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif 7ee8bb9677 build: deprecate ZEPHYR_GCC_VARIANT
We want to support other toolchain not based on GCC, so the variable is
confusing, use ZEPHYR_TOOLCHAIN_VARIANT instead.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-13 07:44:45 -08:00
Marti Bolivar b4842d5339 doc: boards: xtensa: convert make to cmake
Use zephyr-app-commands appropriately.

Signed-off-by: Marti Bolivar <marti@opensourcefoundries.com>
2017-11-10 18:35:50 -05:00
David B. Kinder 62a0cd246d doc: fix uses of back quotes in documentation
ReST defines interpreted text roles where text enclosed by single quotes
can be "intrepreted", for example :ref:`some name` becomes a link to
a label anywhere in the doc set named "some name", :c:func:`funcname()`
becomes a link to the API documentation for "funcname", and
:option:`CONFIG_NAME` becomes a link to, in our case, the documentation
for the generated Kconfig option.

This patch fixes uses of `some name` (without a role) by either adding
an explicit role, or changing to ``some name``, which indicates inline
code block formatting (most likely what was intended).

This is a precursor to changing the default behavior of interpreted
text to treat `some name` as :any:`some name` (as configured in
doc/conf.py), which would attempt to create a link to any available
definition of "some name".

We may not change this default role behavior, but it becomes an option
after the fixes in this patch.  In any case, this patch fixes incorrect
uses of single-quoted text (possibly introduced because GitHub's
markdown language uses single-quoted text for inline code formatting).

Jira: ZEP-2414

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-08-03 11:08:23 -04:00
David B. Kinder 342bdda760 doc: spelling fixes in samples/ and boards/
regular spelling check on .rst files

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-06-12 18:28:08 -04:00
David B. Kinder 2f41cb8329 doc: misspelling and UTF-8 fixes
More general spelling fixes, and cleaning up stray UTF-8 characters
such as curly-quotes, em- and en-dashes.  Use replacement strings
for |reg| and |trade|.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-05-09 20:15:49 -04:00
Mazen NEIFER 37352c809e xtensa port: Added documentation for xt-sim board.
Issue: ZEP-1899

Change-Id: I4cf2878468e8c1c9703a2af13d9c2b3ac6f78042
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-20 21:07:15 +00:00