Commit Graph

12 Commits

Author SHA1 Message Date
Julien Delayen f540cbc5c5 power: Add ARC power states and update sample
Add Low Power States support to the power shim layer
and show the usage in the quark_se sample.

States are defined as follow:
- SYS_POWER_STATE_CPU_LPS: SS2 with LPSS enabled
- SYS_POWER_STATE_CPU_LPS_1: SS2 with LPSS disabled
- SYS_POWER_STATE_CPU_LPS_2: SS1 with LPSS disabled

Jira: ZEP-994

Change-Id: Ie4b93f6e539cb53fc035be00280b66b2cb0d9fea
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-11-11 03:28:54 +00:00
Chuck Jordan db6adc6d2e int: Set default ARC interrupts to lowest priority to start
The code was setting the interrupt priority to 1 for each
vector to start. But I think it might be more appropriate
to set it to the LOWEST priority. Some ARCs will have
upwards to 15 priorities.

Change-Id: I9330ec8df323fe04ba0751faaafa39694f012364
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-06-09 00:34:03 +00:00
Chuck Jordan 4ad41d8d7f arc: early init should invalidate d-cache and set vector table
Some ARC targets can have a data-cache. Although there is no special
instruction to clear exceptions during early init, it is necessary to
invalidate the d-cache BEFORE any data is fetched. The ARC on arduino 101
doesn't have d-cache, and will thus skip this d-cache invalidate.

Also, it is important to set the vector table base register to point to
the interrupt vector table EARLY, so that if an exception is encountered,
the correct vector table is found. Set this base only if it is found to be
different from the one compiled in to the code.
These initialization steps assure that proper exception handling
is in place during early init.

Change-Id: Ie8b5928e5813e104680a6d6510c85d32dc8ed8f3
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-11 11:10:52 +00:00
cjordan 42f7741712 drivers/interrupt_controller: initialize only NUM_IRQS interrupts
Change-Id: I33b4d09bc9255ab75bd25ef8938fc37e74e81038
Signed-off-by: cjordan <cjordan@synopsys.com>
2016-05-04 14:55:10 +00:00
Anas Nashif 275ca60b08 Fixed file description and applied doxygen style
Removed old style file description and documnetation and apply
doxygen synatx.

Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:58 -05:00
Dan Kalowsky 2a57d02400 checkpatch: warning - spacing
Change-Id: Ia63d6c9d8d3c1bd9c540a039263cb8507af82b1e
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:35 -05:00
Dan Kalowsky e4bb957a00 checkpatch: error - pointer_location
Change-Id: I9ce224cb75ba21caecffd6747833257f748b5ecf
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:31 -05:00
Javier B Perez Hernandez f7fffae8aa Change BSD-3 licenses to Apache 2
Change all the Intel and Wind River code license from BSD-3 to Apache 2.

Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:29 -05:00
Dirk Brandewie 0a7e4d1b9b Fix arc interrupt configuration
The _ARC_V2_IRQ_VECT_BASE register must be set to the vector table in
flash.

Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Change-Id: Ied5451c98222f545cd669967023aef26c3d8e48e
2016-02-05 20:15:35 -05:00
Anas Nashif f367f071b6 doxygen: add @brief and capitalize
Remove function name from comment and add @brief instead.
Also capitilize first letter.

Change-Id: Ib708b49bf02e5bc89b0066637a55874e659637e0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:33 -05:00
Anas Nashif 1362e3c162 doxygen: RETURNS: -> @return
Previous comment style used RETRURNS:, use @return to comply
with javadoc style.

Change-Id: Ib1dffd92da1d97d60063ec5309b08049828f6661
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:32 -05:00
Anas Nashif 08f8b65f25 arc: move interrupt controller to drivers/
Change-Id: I731c99062f4b5d2d4d1eb6a3c546ed5f3e494fa4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00