Commit Graph

7 Commits

Author SHA1 Message Date
Erwan Gouriou dbc3c02452 dts: stm32: Populate gpio nodes for stm32f1 series
Introduce gpio nodes in stm32f1 dtsi files

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-04-13 08:56:47 -05:00
Kumar Gala 37d72bf0d6 dts: Update soc-nv-flash nodes
Where missing add compatible = "soc-nv-flash".  Also added a label for
all the soc-nv-flash that we might use in the future.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-23 12:16:53 -06:00
Yannis Damigos 2e3983512a dts: arm: st: Add SPI nodes
This commits adds the "least common denominator" in the
stm32fX.dtsi files and fills the additional SPI nodes
in stm32fXYZ.dtsi files, only for the SOCs where boards
use the additional SPI peripheral.

We could add the rest SPI nodes in the stm32fXYZ.dtsi
files when we add SPI support to other boards.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-17 11:51:48 -06:00
Yannis Damigos ba502927a3 dts: stm32f1: Fix pinctrl node base address
Fixes: #5085

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-11-21 06:57:50 -05:00
Kumar Gala 99c19c62e1 i2c: stm32: Remove usage of CONFIG_I2C_x_DEFAULT_CFG
Stop using CONFIG_I2C_x_DEFAULT_CFG to get the initial value.  Since we
only support master mode we always default to it for initial config and
we get the bitrate from the device tree.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-08-16 10:03:34 -05:00
Erwan Gouriou 368fbafffd dts: arm: stm32f1: Add pinctrl node and uart pin information
Add needed uart pinctrl configuration in pinmux node.
Populate stm32 f1 based boards dts files with references
to uart pinctrl nodes

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-26 15:16:52 -05:00
Erwan Gouriou 851efe0cc6 dts: arm: st: Factorize STM32F1 series soc dtsi files
In order to simplify maintenance of dts files for
stm32f1 series, introduce a stm32f1.dtsi file which
represent the smallest common denominator of IPs in
the family.
Besides, stm32f103Xe includes stm32f103xb, as it is a
extension of this SoC.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-25 10:10:32 -05:00