In preparation for introducing a warning.
Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.
Suggested by Kumar Gala.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The PPB, Peripheral, and any other I/O regions have been
removed, the Shareable options are only important with
unlocked dual cores. Just use the background mapping,
which is RWX for supervisor and no access for user mode.
The flash region needs to be kept to indicate read-only
policy. The RAM regions need to be kept to disable execution.
Fixes#6896
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
When we included SoC specific Kconfig files we do something like:
gsource "arch/arm/soc/arm/*/Kconfig.soc"
However, we should do that inside an if block for that SoC family so as
to limit SoC family specific options to only being visible when that SoC
family is selected. So we simply move the gsource and related items
inside the if SOC_FAMILY_<SOC> block.
Fixes: #7452
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
'cell_string' yaml attribute has been introduced in order to
help enforcement of specific string during defines generation.
This adds complexity in understanding script behavior as a black
box and create additional dependency which is not strictly required.
For node specific generation functions (pinctrl and interrupts),
this could be replaced directly by an hardcoded version
(as everyone used the same 'cell_string' anyway).
For extract_cells functions, string could be replaced by extracted
property name. As a consequence, we're now able to generate defines
for properties refering to these controllers via phandle.
For instance, in following node
spbtle-rf@0 {
compatible = "st,spbtle-rf";
reg = <0>;
reset-gpios = <&gpioa 8 0>;
};
We'll be able to generate:
#define ST_STM32_SPI_...LE_RF_0_RESET_GPIOS_CONTROLLER "GPIOA"
#define ST_STM32_SPI_...PBTLE_RF_0_RESET_GPIOS_FLAGS_0 0
#define ST_STM32_SPI_..._SPBTLE_RF_0_RESET_GPIOS_PIN_0 8
Only impact for this whole change is for NXP clocks which were the
only ones using 'cell_string' attribute with a value different than
the default one.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Indexed defines were systematically generated even when there
was only one element to generate.
So we ended up generated a lot of _0 defines.
Then we needed to generate aliases to these _0 indexed defines,
in order to get useful defines.
For instance:
#define GPIO_LEDS_0_GPIO_FLAGS_0 4
#define GPIO_LEDS_0_GPIO_PIN_0 5
#define GPIO_LEDS_0_GPIO_FLAGS GPIO_LEDS_0_GPIO_FLAGS_0
#define GPIO_LEDS_0_GPIO_PIN GPIO_LEDS_0_GPIO_PIN_0
This commit allows to generate _0 indexed define only if a
property has more than one elements to define.
Aliases generation to _0 indexed defines are also removed.
Note: IRQ are left untouched since this is frequent to handle
multiple IRQs in a driver
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds 8 MB and 64 MB flash size options, which correspond to the two
external flashes (qspi flash and hyperflash) on the mimxrt1050_evk
board. Adds a 32 MB SRAM size option, which corresponds to the external
sdram on the board.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Until now, Zephyr has used a patched Kconfiglib that turns 'source' into
a globbing source (by replacing 'source' with 'gsource' at the token
level). There's two problems with this:
- The patch needs to be maintained separately
- Misspelled filenames are silently ignored, as they look like glob
patterns that don't match anything
Fix it as follows:
1. Replace all 'source' statements that use wildcards with 'gsource'
2. Remove the custom Kconfiglib patch so that 'source' no longer globs
The sed pattern '/source.*[*?]/s/source/gsource/' was run over all
Kconfig* files to do the replacement.
source's that use environment variables that might contain glob patterns
were manually changed to gsource.
Building the docs in doc/ is a good test, as doc/Makefile deliberately
sets the environment variables to glob up as many Kconfig files as
possible.
Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
It seems like SEGGER is supported across all the NXP SoC families so
lets enable it across all of them.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual
Cortex A7 core and Single Cortex M4 core.
Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A7 core (running Linux) via RPmsg.
The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README
The A7 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A7 can perform these steps at bootloader level after the Linux
system has booted.
The M4 can use up to 5 different RAMs. These are the memory mapping for
A7 and M4:
+---------------+-----------------+---------------------------+
| Memory Name | Start Address | Size |
+===============+=================+===========================+
| TCML | 0x007F8000 | 32KB |
+---------------+-----------------+---------------------------+
| TCMU | 0x20000000 | 32KB |
+---------------+-----------------+---------------------------+
| OCRAM_S | 0x20180000 | 32KB |
+---------------+-----------------+---------------------------+
| OCRAM | 0x00900000 | 128KB |
+---------------+-----------------+---------------------------+
| DDR | 0x10000000 | 256MB |
+---------------+-----------------+---------------------------+
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
Clean up Kconfig so each SoC just selects the specific Cortex-M
implementaiton rather than having to select both CORTEX_M and
CORTEX_{M0, M3, M4, etc.}.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move common SoC dts.fixup defines into arch/arm/soc/nxp_imx/rt/dts.fixup
so we remove duplication in the boards and only have board specific
defines in boards/arm/<FOO>/dts.fixup.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Unlike other NXP SoCs currently in Zephyr, the mimxrt1052 has the ARM
MPU rather than the NXP MPU. Start out by enabling it with a simple set
of memory regions for "flash" (ITCM), "ram" (DTCM), and the peripheral
buses. More regions will need to be added when we implement support for
external memories.
Tested with:
- samples/mpu/mpu_stack_guard_test
- tests/kernel/mem_protect/protection
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and
series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core,
512 KB TCM, and many peripherals including 2D graphics, an LCD display
controller, camera interface, SPDIF and I2S. Unlike other SoCs in
Zephyr, the mimxrt1052 has no internal flash.
This initial port to mimxrt1052 configures the system clock to operate
at 528 MHz, and enables the serial/uart and gpio interfaces to support
the hello_world and blinky samples. Support for additional Zephyr driver
interfaces will come later.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Ulf Magnusson