Until now iterable sections APIs have been part of the toolchain
(common) headers. They are not strictly related to a toolchain, they
just rely on linker providing support for sections. Most files relied on
indirect includes to access the API, now, it is included as needed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
New silicon revision supports reading of GPIO inputs.
Button added to shield overlay to support new functionality.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
- The boards\arm\cy8cproto_063_ble board now has ADC enabled
- This includes overlay files for the test app and sample app
Signed-off-by: Bill Waters <bill.waters@infineon.com>
The link to the default KConfig for CY8CPROTO-063-BLE in the board's
index.rst is broken and leads to a HTTP 404 error.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Convert the NPCX keyboard scan driver to the input subsystem and add the
input to kscan compatibility driver to maintain functionality with the
current API.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
intel_adsp_ace20_lnl can also build with intel_adsp_ace15_mtpm
toolchain in Zephyr SDK as the SoC is quite similar. This allows
twister to build in CI to avoid any breakage.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit sets the DCACHE_LINE_SIZE config for all xtensa-based
NXP SoCs for SOF usage.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit sets the DCACHE_LINE_SIZE config for all xtensa-based
Intel SoCs for SOF usage.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
according to schematics and NXP's sample code, the correct PIN for the
PWDN pin is iomuxc_gpio_ad_b1_02_gpio1_io18
Signed-off-by: Michele Balistreri <michele@bitgamma.com>
Include UF2 runner for the XIAO BLE to allow basic flashing over UF2
without any additional hardware.
Tested with both `xiao_ble` and `xiao_ble_sense` boards.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
1. Enable os_timer as a wakeup-source in the board
dts file.
2. Enable PM_DEVICE when PM is enabled.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Actual DCCM size is 100000 in nsim_hs_mpuv6, nsim_hs
and nsim_hs3x_hostlink, but their nsim property is
40000. Now fixed the difference to avoid data access
to unpopulated region during picolibc malloc heap init.
In minimal libc, it is set not using malloc as default.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
This commit updates the qemu_x86_tiny linker script to place the
Newlib-nano text and rodata sections into the corresponding pinned
sections so that they are accessible.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds BLE support to the `efr32xg24_dk2601b` board. It also
modifies the SiLabs BT HCI driver to accomodate the EFR32xG24 SoC
series.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
900us regulator startup time was chosen based on tests with single board,
when used directly after 'jlink' flash runner.
It seems that this is not enough when board is reset using RESET button.
Additionally some boards require even more startup time in order to
successfully communicate with LSM6DS3TR-C IMU.
Increase regulator startup time from 900us to 3ms, which seems to be good
enough.
Reported-by: Matthew MacGregor <matthew.macgregor.g@gmail.com>
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
board:
- update device tree to use flexcomm devices to the chip design
- enable clocks (soc init file)
- setup connections for loopback test in system controller (board init
file)
tests:
- update board files (overlay, conf)
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Add green_pwm_led
Tested using samples/basic/fade_led/
Updated mimxrt1060_evkb.dts as FLEXPWM not routed to LED on this EVK
Signed-off-by: Maxin John <maxin.john@gmail.com>
When building for mimxrt1050_evk_qspi board, runners.yaml needs
to have the pyocd arg target set to mimxrt1050_quadspi so that
west knows to access Quad SPI instead of hyperflash.
Signed-off-by: Jim Norton <notronrj@gmail.com>
Some users use this simulated board interactively
(even though it is not recomended).
In that case, they may want to perceive a relatively smooth
time flow.
By default the maximum resynchronization offset is set at
1 second.
When running with a simulation speed close to real time,
this results in the simulated board jerking and pausing in
time 1 second at a time when there is no radio activity.
With this new option, users can set a resynchronization
offset of, for ex., 10 ms, which would give the illusion
of time progressing smoothly.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The latest Yocto release, PD23.1.0, has the CACHE_CMD included.
Therefore, the default image can be used to boot Zephyr.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Effort has been made to abstract the features that are common
to both the Pico and Pico W into a shared file when possible.
This commit does not include the addition of bluetooth or wifi
drivers for the W's Infineon module.
Signed-off-by: Dave Rensberger <davidr@beechwoods.com>
Add support for partial refresh profiles. This makes it possible to
use partial refresh on generation 2 devices which are able to store
partial refresh LUTs in OTP.
Partial refresh is only enabled if a partial profile has been
provided. The display will use the full refresh profile if in this
case.
Devices that need custom LUTs and voltages can specify them separately
for the full and partial profiles. The controller will be reset when
changing profiles which means that profiles always override the
default reset values. This means that it is, for example, possible to
use default values and LUTs from OTP for a full refresh and a custom
profile for partial refreshes.
For example, to use a GoodDisplay GDEY027T91 with partial refresh
simply use the following device tree fragment:
display: ssd1680@0 {
compatible = "solomon,ssd1680";
spi-max-frequency = <4000000>;
duplex = <SPI_HALF_DUPLEX>;
reg = <0>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>;
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>;
/* Enable the built-in temperature sensor */
tssv = <0x80>;
width = <264>;
height = <176>;
/* Enable partial refresh using built-in LUT */
partial {
};
};
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Update the device tree bindings for the SSD16xx driver to make it
possible to specify multiple refresh profiles.
The only profile currently supported is the 'full' profile.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The SSD16xx driver currently provides basic support for most chips in
the Solomon Systech SSD16xx range of e-paper drivers. We currently use
the SSD1608, SSD1673, SSD1675A, and SSD1681 in various boards
supported by Zephyr.
The main user-facing difference between the various SSD16xx chips is
the resolution they support (sources & gates), but there are other
differences as well. For example:
* 8 or 16 bits used to represent x coordinates
* 8 or 16 bits used to represent y coordinates
* Differences in refresh configuration (SSD16XX_CMD_UPDATE_CTRL2)
* Differences in LUT sizes
The driver currently assumes that the user specifies the number of
bits used to describe coordinates. However, as we add support for more
chips, more of the differences will become apparent and need
workaround.
Comparing data sheets from different chips in the SSD16xx range
suggests that there are (at least) two different generations
present. These differ in the size of the LUTs they expect and the way
they handle partial refresh. This impacts register layout where
SSD16XX_CMD_UPDATE_CTRL2 uses bit 3 selects "mode 2" whereas older
devices uses this for a mode referred to as "initial".
In order to add support for partial refresh in newer devices, we need
to be able to distinguish between the different generations of the
chip. It might be possible to add a DT property to indicate the
revision, but that seems like a bit of an anti-pattern and it would be
hard for users to specify the correct chip generation.
This change introduces chip-specific compatible strings instead of the
generic SSD16xx. There is unfortunately clear pattern that can be used
to distinguish different generations, so the full chip name must be
specified. A benefit of this is that we don't need to specify the
width of the fields describing coordinates in device trees.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Move the pinctrl dtsi (mimx8ml8dvnlz-pinctrl.dtsi) from board dts to
_uart overlay since, now, for nxp_adsp_imx8m, this is used only with
uart support for certain samples.
This also fixes a build error on SOF, where we don't take the nxp_hal
and the dtsi cannot be found.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Add support for SPI on RT1040 EVK, tested using
tests/drivers/spi/spi_loopback sample. Transfers are enabled using DMA
mode, with LPSPI1.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable ADC support for RT1040 EVK. Tested using samples/drivers/adc,
using channels 3 and 4 of ADC0.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enabled PWM output on J16.6, using tests/drivers/pwm/pwm_api.
This board does not connect a PWM output to an LED, so only
the PWM testcase was verified to function.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add RT1040 EVK board definition. This board port currently enables
UART and GPIO only. Programming is supported by JLink host tools.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
All ESP32 boards shows a garbage char before Zephyr banner.
This happens during uart TX pin configuration that current
lacks setting as output high.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
add dma supported on board nucleo_h743zi.
the twister test is now enable for tests/drivers/adc/adc_dma on board
nucleo_h743zi.
used on driver st_stm32_adc with CONFIG_ADC_STM32_DMA=y.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Update LTDC driver to use LCDIF bindings, to simplify bindings
between LCD interface controller IP blocks.
Boards supporting the LTDC are also updated to use the properties as
declared by the new lcd controller binding
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.
Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.
Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add the alias to the MX25LM512 octo-NOR flash for the spi-flash node.
Remove the overlay for the samples/drivers/spi_flash as no MDMA driver
exists yet for the stm32h7.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Currently, the usb_dc_dw driver is not enabled for any platform.
Allow to build the driver for cyclonev_socdk. Subsequent patches
will allow the driver to be used on additional platforms.
Enable USB device controller and use use new snps,dwc2 compatible.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add GDMA support for esp32s3.
Remove suspend/resume since they are optional and do
the same as start/stop.
Fix possible null pointer derreference.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Declare SCB nodes to be used as UART/SPI/I2C by the boards, Move
common declarations from psoc6_02 to the parent dtsi file
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Gerard Marull-Paretas