Commit Graph

33 Commits

Author SHA1 Message Date
Andy Ross a0dd2de6fd xtensa: Remove _xt_set_exception_handler()
This was a dead API.  Nothing ever used it, it wasn't exposed in any
API headers.  It never appeared in documentation.  It's not
particularly clear why a Zephy app would want to hook
architecture-specific exceptions instead of simply using the portable
error framework anyway. And it's not supported by asm2.  Delete.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross 042d8ecca9 kernel: Add alternative _arch_switch context switch primitive
The existing __swap() mechanism is too high level for some
applications because of its scheduler-awareness.  This introduces a
new _arch_switch() mechanism, which is a simpler primitive that looks
like:

    void _arch_switch(void *handle, void **old_handle_out);

The new thread handle (typically just a stack pointer) is specified
explicitly instead of being picked up from the scheduler by
per-architecture code, and on return the "old" thread handle that got
switched out is returned through the pointer.

The new primitive (currently available only on xtensa) is selected
when CONFIG_USE_SWITCH is "y".  A new C _Swap() implementation based
on this primitive is then added which operates compatibly.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross a34f884f23 xtensa: New asm layer to support SMP
SMP needs a new context switch primitive (to disentangle _swap() from
the scheduler) and new interrupt entry behavior (to be able to take a
global spinlock on behalf of legacy drivers).  The existing code is
very obtuse, and working with it led me down a long path of "this
would be so much better if..."  So this is a new context and entry
framework, intended to replace the code that exists now, at least on
SMP platforms.

New features:

* The new context switch primitive is xtensa_switch(), which takes a
  "new" context handle as an argument instead of getting it from the
  scheduler, returns an "old" context handle through a pointer
  (e.g. to save it to the old thread context), and restores the lock
  state(PS register) exactly as it is at entry instead of taking it as
  an argument.

* The register spill code understands wrap-around register windows and
  can avoid spilling A4-A15 registers when they are unused by the
  interrupted function, saving as much as 48 bytes of stack space on
  the interrupted stacks.

* The "spill register windows" routine is entirely different, using a
  different mechanism, and is MUCH FASTER (to the tune of almost 200
  cycles).  See notes in comments.

* Even better, interrupt entry can be done via a clever "cross stack
  call" I worked up, meaning that the interrupted thread's registers
  do not need to be spilled at all until they are naturally pushed out
  by the interrupt handler or until we return from the interrupt into
  a different thread.  This is a big efficiency win for tiny
  interrupts (e.g. timers), and a big latency win for all interrupts.

* Interrupt entry is 100% symmetric with respect to medium/high
  interrupts, avoiding the problems seen with hooking high priority
  interrupts with the current code (e.g. ESP-32's watchdog driver).

* Much smaller code size.  No cut and paste assembly.  No use of HAL
  calls.

* Assumes "XEA2" interrupt architecture, the register window extension
  (i.e. no CALL0 ABI), and the "high priority interrupts" extension.
  Does not support the legacy processor variants for which we have no
  targets.  The old code has some stuff in there to support this, but
  it seems bitrotten, untestable, and I'm all but certain it doesn't
  work.

Note that this simply adds the primitives to the existing tree in a
form where they can be unit tested.  It does not replace the existing
interrupt/exception handling or _Swap() implementation.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Anas Nashif 11a9625eaf debug: remove DEBUG_INFO option
This feature is X86 only and is not used or being tested. It is legacy
feature and no one can prove it actually works. Remove it until we have
proper documentation and samples and multi architecture support.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-12 13:58:28 -08:00
Ramakrishna Pallala 301acb8e1b kernel: include: rename nano_internal.h to kernel_internal.h
Rename the nano_internal.h to kernel_internal.h and modify the
header file name accordingly wherever it is used.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-01-31 10:07:21 -06:00
Youvedeep Singh 833025dd94 timer: xtensa_sys_timer: Tickless Kernel Implementation for Xtensa
Implement Tickless Kernel support for Xtensa Architecture.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2017-11-07 08:17:40 -05:00
Anas Nashif 780324b8ed cleanup: rename fiber/task -> thread
We still have many places talking about tasks and threads, replace those
with thread terminology.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-30 18:41:15 -04:00
David B. Kinder 4600c37ff1 doc: Fix misspellings in header/doxygen comments
Occasional scan for misspellings missed during PR reviews

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-10-17 19:40:29 -04:00
Andrew Boie 74afcb67ae arches: move _NanoFatalErrorHandler defintion
This needs to be in <arch/cpu.h> so that it can be called
from the k_panic()/k_oops() macros in kernel.h.

Fixes build errors on these arches when using k_panic() or
k_oops().

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-18 09:34:23 +03:00
Leandro Pereira 4ca586e62d arch: xtensa: Use Zephyr configuration options
Unconditionally use CONFIG_SIMULATOR_XTENSA to determine if XT_SIMULATOR
or XT_BOARD should be defined.

If CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, also define XT_CLOCK_FREQ.  This
isn't ideal as the clock frequency might be changed in runtime and this
effectively makes it a constant.

Until we can control the clock frequency in runtime, this will suffice.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Anas Nashif 397d29db42 linker: move all linker headers to include/linker
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-18 09:24:04 -05:00
Andrew Boie 99c89e17e3 xtensa: fix coprocessor save area
A bad rebase of a patch that moved these defines around
unintentionally reverted a necessary change to the coprocessor
save area.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 12:47:23 -04:00
Andrew Boie 73abd32a7d kernel: expose struct k_thread implementation
Historically, space for struct k_thread was always carved out of the
thread's stack region. However, we want more control on where this data
will reside; in memory protection scenarios the stack may only be used
for actual stack data and nothing else.

On some platforms (particularly ARM), including kernel_arch_data.h from
the toplevel kernel.h exposes intractable circular dependency issues.
We create a new per-arch header "kernel_arch_thread.h" with very limited
scope; it only defines the three data structures necessary to instantiate
the arch-specific bits of a struct k_thread.

Change-Id: I3a55b4ed4270512e58cf671f327bb033ad7f4a4f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-26 16:29:06 +00:00
Kumar Gala bf53ebf2c8 arch: convert to using newly introduced integer sized types
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.  There are few places we dont convert over to the new
types because of compatiability with ext/HALs or for ease of transition
at this point.  Fixup a few of the PRI formatters so we build with newlib.

Jira: ZEP-2051

Change-Id: I7d2d3697cad04f20aaa8f6e77228f502cd9c8286
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 12:08:12 +00:00
Kumar Gala 789081673f Introduce new sized integer typedefs
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t.  This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.

We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.

We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.

Jira: ZEP-2051

Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-20 16:07:08 +00:00
Mazen NEIFER 01e9646638 xtensa port: Clear the CP descriptor of new created thread.
This commit should fix the concern about uninitialized memory of main
thread that was raised in https://gerrit.zephyrproject.org/r/#/c/12920/

The issue is more general, if it happens that the content of the
CPENABLE flag of any thread is set then any other thread using the CP
may cause a memory corruption.

I'd prefer to avoid the issue by initializing the CP descriptor to 0.
The descriptor itself is few words. We set them to 0 up to CP_ASA, which
is set to a real value.

As the dummy thread instantiated at the kernel startup does not use CP,
there is no CP area in its thread memory buffer. However it is mandatory
that it have the CP descriptor and that cpEnable in that descripot is
set to null. This is ensured by adding XT_CP_DESCR_SIZE to
_K_THREAD_NO_FLOAT_SIZEOF.

Change-Id: I6a36b5b363600ea1e6d98ab679981182b2b5a236
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-20 16:01:55 +00:00
Anas Nashif 8df439b40b kernel: rename nanoArchInit->kernel_arch_init
Change-Id: I094665e583f506cc71185cb6b8630046b2d4b2f8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-19 10:59:35 -05:00
Mazen NEIFER a6e0404983 xtensa port: Fixed crash on startup on CP enabled cores
The issue was that cpStack was changed to a memory buffer by commit
https://gerrit.zephyrproject.org/r/#/c/12816
However the assembly code was expecting it to be a pointer and thus
issuing an indirection, that leads to wrong addresses.

The fix removed this unnecessary indirection and thus the inherent
invalid memory access exception.

Issue: ZEP-1997
Change-Id: I843f049212f2d116a01b05367a284209f463a5e7
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-13 11:54:49 -07:00
Mazen NEIFER cc8ffbdb44 Xtensa port: Moved coporcessor context area inside struct _k_thread
The CP context area was before on the bottom of the stack just
after the thread descriptor. Now it is moved inside the thread
descriptor to support some kind of memory protection.

Change-Id: Id3ebeaecfd9c2475899713fdc8da583a1f9121f9
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-11 00:05:27 +00:00
Anas Nashif b84dc2e124 kernel: remove all remaining references to nanokernel
Change-Id: I43067508898bc092879f7fe9d656ccca6fd92ab2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-10 20:21:10 +00:00
Anas Nashif d7bc60f096 kernel: remove remaining microkernel references
Change-Id: Ie648dbaaf714316c21395bd43e555618013dbd19
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-10 20:21:05 +00:00
Andrew Boie 5c9f7e28a1 xtensa: remove legacy kernel cruft
fibers/tasks are now just threads and we should not be using
struct *tcs any more.

Change-Id: Iee5369abcc66b4357a0c75537025fe8edb0ffbb4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-03 16:40:48 +00:00
Andrew Boie 42562b9367 xtensa: fix numerous checkpatch issues
Change-Id: I903f5f0692849fb9e7bf5d978b63b12bf1bd6e33
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:03 -08:00
Mazen NEIFER fb5299cd4a Xtensa port: Removed trailing spaces and unused macros. Reformatted comments.
Change-Id: I7f3fcba5d78c153c9b2830982e3ed6d5a1150c78
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:03 -08:00
Mazen NEIFER aacfd63331 Xtensa port: Removed duplicate file and renamed to sys_io.h as other platforms.
Change-Id: I293bfa9ff8c5e641c727612c56968cec901dbfec
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER bb038cc1be Xtensa port: Fixed function setting Sawp return value.
The retval field shall hold the return value itself not a pointer on its
location.

Change-Id: I3f9e225f2bdd501f88441946b5187ebbd17a71e3
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER 93e53da56a Xtensa port: Removed warnings related to function _NanoFatalErrorHandler.
This function needs to be decalred in a file included by _thread_entry.
It also needs to have exit function declared as not returning.

Change-Id: I2a01e7408cf70266351ae5089f45b5d9d009fabe
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER 7c75da1e1a Xtensa port: Added missing initalization of thread base sturct in _new_thread.
Change-Id: Icf9e1e6d5f831c2cf6e1262c6f8e1a46356edfe7
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER e4e3cf604e Xtensa port: Added Xtensa specific code (C + S) files.
Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Andrew Boie aa3ab35c88 xtensa: fixup license identifiers
Master branch changed requirements for license headers while this
branch has been in development.

Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER 49b3c0028d Xtensa port: Added fields offset support for kernel and thread structures.
Change-Id: I9cc44f60757a2f988e2a6341da9591a5e5f54561
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER 71b884b658 Xtensa port: Added Xtensa header generic files.
Change-Id: Ia2202080d09008fbfd4e803cd5266aa8caa16388
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER b78ceec452 Xtensa port: Added kernel arch dependent structs and functions.
Change-Id: I8b35454cdaac0087b7b68b96e6ec1780c71b1e9d
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00