zephyr

Commit Graph

Author	SHA1	Message	Date
Filip Kokosinski	6299890b0e	dts: riscv32: microsemi-miv: add flash and sram Add flash and SRAM to the Microsemi MiV device tree. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>	2019-05-10 10:34:31 -05:00
Nathaniel Graff	8907c09fee	soc/miv: Use DTS to generate PLIC addresses Describe the MMIO register regions for the PLIC in the DTS instead of hardcoded in soc.h. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>	2018-12-04 07:48:27 -06:00
Kumar Gala	11cb8778c7	riscv: Add min dts support for miv SoC & m2gl025_miv board Add minimal DTS support for the m2gl025_miv. The dts just has the core, SoC, PLIC, and UART described. We still get memory related info from Kconfig. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>	2018-11-03 06:58:23 -04:00

Author

SHA1

Message

Date

Filip Kokosinski

6299890b0e

dts: riscv32: microsemi-miv: add flash and sram

Add flash and SRAM to the Microsemi MiV device tree.

Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>

2019-05-10 10:34:31 -05:00

Nathaniel Graff

8907c09fee

soc/miv: Use DTS to generate PLIC addresses

Describe the MMIO register regions for the PLIC in the DTS instead of
hardcoded in soc.h.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>

2018-12-04 07:48:27 -06:00

Kumar Gala

11cb8778c7

riscv: Add min dts support for miv SoC & m2gl025_miv board

Add minimal DTS support for the m2gl025_miv.  The dts just has the core,
SoC, PLIC, and UART described.  We still get memory related info from
Kconfig.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

2018-11-03 06:58:23 -04:00

3 Commits