Add PCI device IDs for common Intel Raptor Lake variants and Alder Lake N.
These all have cAVS2.5 audio DSP.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Numerically sort the PCI DIDs for cAVS2.5 hardware. This follows
the convention in e.g. Linux and coreboot and eases maintainance. No
functional change.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The "Detected cAVS 1.8+ hardware" message is misleading as it implies
some version of Intel cAVS hardware has been found, while in fact this
script supports also other types of hardware, including Intel ACE.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Clean up code documentation to drop references to platforms no longer
supported in the code. Continues the cleanup started in commit
086e4f84ed ("intel_adsp: cavstool: Remove
legacy code").
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The default configuration for PINCTRL should not be set with
the other default configurations in .defconfig, instead select
a default value as part of defining the UART driver.
Signed-off-by: Andrew Davis <afd@ti.com>
Add initial SoC support for the TI J721E SoC series Cortex-R5 core.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
The commit introduced regression for hsdk4xd platform.
The hsdk4xd SoC setup from soc_early_asm_init_percpu need to be done
in early code before any C code execution.
The current approach has multiple issues
- we call function (which can be easily implemented in C for
this or other SoC) from the place where we haven't setup stack
pointer (so we can't use stack) - which is very error-prone
- we never return back from soc_reset_hook on hsdk4xd platform
So let's just revert it for now. If any other ARC SoC need to use
soc_reset_hook - than it can be implemented properly.
This reverts commit 8c32a82e47.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Series 2 always uses the device init HAL, while Series 0/1 never do.
Create a separate soc.c for Series 2 to make both versions easier to read.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Swap from the deprecated device_init_* functions to clock manager
for clock tree configuration. Populate config headers using
device tree representation of clock tree and oscillator config.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Switch EFR32MG21 to use the device init HAL. This makes the init sequence
the same as the rest of Series 2.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
On Series 2, set the SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option from
DeviceTree, rather than separately configuring it in board-level
defconfig.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Defconfig was only available at the vendor and series level,
make it possible to have family specific definitions too.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The DC-DC converter was unconditionally initialized with default
settings on Series 2. Add device tree binding and nodes, and guard
call to init function. Map DT options to config header from HAL.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
- add ITCM definitions (for LinkServer) in board.cmake
- update of soc.c to support RAM images (stack pointer)
- doc update
Change applies to both versions of the MIMXRT1170 EVK
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Extracts the max32 flashprog linker section to a dedicated linker script
that is conditionally included only when the flash driver is enabled.
This prepares max32 soc family to set SOC_LINKER_SCRIPT directly to the
common arm cortex-m linker script.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
This commit enables PMP on 64-bit SoCs from the SiFive Freedom SoC series
by default.
This change is needed to e.g. run the Userspace Hello World demo.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Added a new driver to support SPI communication via EUSART. Since the
Silabs EFR32MG24 family SoCs have only one USART, EUSART support is
necessary for implementing SPI functionality.
Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
support the configurations which apply for LVDS pads
+ termination resistor
+ current reference control
+ rx current boost
Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
IMXRT1062 bootrom reads boothdr initial vector table
from 0x60001000. In the CMAKE scatter linker scripts we put multiple
sections at offset 0x1000 in the rom. In linkers other than LD, we are
not guaranteed a particular order when placing these.
If we specify FIRST we can count on the .ivt coming first. The other
positions aren't as crucial.
From IMXRT1060RM.pdf 9.7.1
> The location of the IVT is the only fixed requirement by the ROM.
> The remainder or the image memory map is flexible and
> is determined by the contents of the IVT.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
The production version of the nRF54L15 SoC is now available, so remove
the initial Engineering A (EngA) preview version.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This config will be used to indicate if a platform
has the support for monolithic BT feature.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
New PDM, some present on nRF54L15 FP1, instances have
been added. Modified condfiguration file for nRF5340,
which now requires PDM0 instance.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
- Disables on reset NMI and EzPort.
- Fixes frdm-k64 SW3 user button on reset issue.
So it can be assigned to the mcuboot-button0 alias.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
ETR handler (for Coresight STM logging) is using console UART and
can act as the shell backend. When that happens default serial shell
backend shall be disabled (and it is by default enabled if there is
a zephyr,console chosen set.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This commit applies several changes in the way "heap_runtime"
feature is used. It can't be split due to bisectability issues.
Whenever the feature is enabled, a new heap is created and
custom malloc/calloc/free functions are added into the build
system. Those functions are currently used for internal Wi-Fi and BLE
drivers only.
Such changes are described below:
1) Rename heap.c to esp_heap_runtime.c for better readability.
2) Rename RUNTIME_HEAP to HEAP_RUNTIME to make it similar to what is
available in Zephyr.
3) Add runtime heap to BT as such as Wi-Fi.
Fixes#79490Fixes#79470
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This is a follow-up to commit 7a2ce2882a.
Do not enable clock control by default on nRF54H Series SoCs when
the system timer is present, because clock control is not needed
for this purpose there.
Add missing `default y` in the CLOCK_CONTROL_NRF2 Kconfig option that
enables compilation of clock control drivers for nRF54H Series.
This way modules that actually require clock control (like drivers
that use radio) will be able to enable it using the generic option
(CLOCK_CONTROL), not the above one that is specific for nRF54H.
Update accordingly applications that referenced the CLOCK_CONTROL_NRF2
option.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Fix definition for ROM status register for ACE1.5. The value should be
same as ACE2.0 and only different for ACE3.0.
Fixes: 6ad9b6ccab ("soc: intel_adsp: tools: add intel_adsp_ace30
support to cavstool.py")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
SOC_FLASH_MCUX has additional dependencies for LPC55xxx CPUs, due to the
fact that the flash should be disabled when executing in nonsecure mode.
Since the merge of HWMv2, this dependency has been set incorrectly at
the SOC level, resulting in the IAP flash driver being enabled when
targeting CPU1, which is incorrect. Fix the Kconfig dependency to
resolve this issue.
Fixes#79576
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enables the XSPIM2 rail when using GPIO bank N
Enables the XSPIM1 rail when using GPIO bank O or P
Enables the USBvoltage detector when using the GPIO M
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Service for powering peripherals that use GPIO pins
in the global power domains:
- Active Fast
- Active Slow
- Main Slow
Signed-off-by: Rafal Dyla <rafal.dyla@nordicsemi.no>
Commit b73c5578e3 ("soc: ti: move init code from SYS_INIT to hooks")
changed SYS_INIT to init hooks. For AM6x M4 target soc_prep_hook()
was added by mistake instead of soc_early_init_hook(), the platform needs
RAT translation initialized before any other operation and the platform
failed to boot with this change, fix this by replacing with
soc_early_init_hook()
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Kai Vehmanen