2 Commits

Author	SHA1	Message	Date
Jean-Paul Etienne	4b8ae8863c	riscv32: riscv-privilege: Platform-Level Interrupt Controller support ... Updated the riscv-privilege SOC family to account for SOCs supporting a Platform-level Interrupt Controller (PLIC) as specified by the riscv privilege architecture. riscv-privilege SOCs supporting a PLIC have to implement the following list of APIs: void riscv_plic_irq_enable(uint32_t irq); void riscv_plic_irq_disable(uint32_t irq); int riscv_plic_irq_is_enabled(uint32_t irq); void riscv_plic_set_priority(uint32_t irq, uint32_t priority); int riscv_plic_get_irq(void); Change-Id: I0228574967348d572afc98a79257c697efc4309e Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>	2017-03-20 23:19:36 +00:00
Jean-Paul Etienne	d1bd80a4a9	riscv32: added the riscv-privilege SOC_FAMILY ... added the riscv-privilege SOC_FAMILY, under which all riscv SOCs supporting the riscv privilege architecture specifcation shall reside. These SOCs shall notably have a common base for handling IRQs. Moved riscv32-qemu under the riscv-privilege SOC_FAMILY Change-Id: I5372cb38e3eaed78886f22b212ab4f881ef30b3f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>	2017-03-20 23:19:35 +00:00