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27,719 Commits 149 Branches 178 Tags 877 MiB
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5 Commits

Author SHA1 Message Date
Anas Nashif c2c6a6a245 qemu_riscv32: use hifive1 configuration 
Use hifive1 configuration for this qemu and set
SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000

Fixes #10043

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
 2018-11-05 11:00:38 -05:00
Kumar Gala 8ded3fb1e2 riscv: Move DTS Kconfig enablement to arch level 
Now that all supported riscv boards support dts, move the Kconfig option
to the arch level.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
 2018-11-03 06:58:23 -04:00
Savinay Dharmappa b7c4c0302c dts: riscv32: riscv32-qemu: Add device tree support 
add device tree support for riscv32-qemu

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
 2018-06-13 08:47:52 -04:00
Anas Nashif dd8fd72826 boards: mark qemu targets with a unified Kconfig 
This will allow checking if we are building for QEMU globally, without
having to know the exact architecture and board name.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
 2017-07-26 07:40:45 -05:00
Jean-Paul Etienne 60030c9a80 boards: added support for the qemu_riscv32 board 
The qemu_riscv32 board makes use of:
1) the uart_riscv_qemu driver
2) the riscv_qemu_timer driver

Change-Id: I413e3990a66bc62a0d15d82ebca6940b381fed43
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
 2017-01-13 19:58:09 +00:00