zephyr

Author	SHA1	Message	Date
Andrew Boie	3aa59a6eed	tests: test dynamic IRQ APIs The gen_isr_table test now tries to install two dynamic IRQ handlers. RISCV32 has a workaround due to limited number of SW triggerable interrupts that can be configured. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>	2018-11-20 09:30:34 -05:00
Anas Nashif	829598be2b	tests: add CONFIG_TEST for marking tests Mark tests with CONFIG_TEST to allow for test specific setup and configuration. Signed-off-by: Anas Nashif <anas.nashif@intel.com>	2018-01-08 10:03:57 -05:00
Andrew Boie	d182d0c298	tests: gen_isr_table: don't set compiler opt Instead, just set -O0 for the particular function which needs it. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>	2017-09-07 16:33:33 -07:00
Andrew Boie	5c335ce55f	tests: gen_isr_table: actually run the IRQ So far, only implemented on ARM. It's not possible to do this on Nios II and RISC-V. Change-Id: I84c8d99cd163dff46de4bc4a7ae40768daf8e4ce Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>	2017-02-15 04:49:18 +00:00
Andrew Boie	122467e9ee	tests: add test for gen_isr_table This test is intended to verify that the SW ISR and vector tables have been populated correctly. Change-Id: Ic7f50c02dc0807d7ddefa710da67f818ff707ad6 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>	2017-02-11 01:28:00 +00:00